Shi Slave Address Register (Hsar)—Dsp Side - Motorola DSP56367 User Manual

being loaded from the shift register. Reading all data from HRX clears the HRNE flag. The
HRX may be read by DSP core instructions or by DMA transfers. The HRX FIFO is reset to
the empty state when the chip is in stop mode, and during hardware reset, software reset, and
individual reset.
9.5.4 SHI SLAVE ADDRESS REGISTER (HSAR)—DSP SIDE
The 24-bit slave address register (HSAR) is used when the SHI operates in the I
and is ignored in the other operational modes. HSAR holds five bits of the 7-bit slave device
address. The SHI also acknowledges the general call address specified by the I
(eight zeroes comprising a 7-bit address and a R/W bit), but treats any following data bytes as
regular data. That is, the SHI does not differentiate between its dedicated address and the
general call address. HSAR cannot be accessed by the host processor.
9.5.4.1 HSAR Reserved Bits—Bits 19, 17–0
These bits are reserved. They read as zero and should be written with zero for future
compatibility.
9.5.4.2 HSAR I
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Part of the I C slave device address is stored in the read/write HA[6:3], HA1 bits of HSAR.
The full 7-bit slave device address is formed by combining the HA[6:3], HA1 bits with the
HA0 and HA2 pins to obtain the HA[6:0] slave device address. The full 7-bit slave device
address is compared to the received address byte whenever an I
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I C bus transfer. During hardware reset or software reset, HA[6:3] = 1011 and HA1 is cleared;
this results in a default slave device address of 1011[HA2]0[HA0].
9.5.5 SHI CLOCK CONTROL REGISTER (HCKR)—DSP SIDE
The HCKR is a 24-bit read/write register that controls SHI clock generator operation. The
HCKR bits should be modified only while the SHI is in the individual reset state (HEN = 0 in
the HCSR).
For proper SHI clock setup, please consult the datasheet. The programmer should not use the
combination HRS = 1 and HDM[7:0] = 00000000, since it may cause synchronization
problems and improper operation (it is an illegal combination).
The HCKR bits are cleared during hardware reset or software reset, except for CPHA, which
is set. The HCKR is not affected by the stop state.
The HCKR bits are described in the following paragraphs.
MOTOROLA
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C Slave Address (HA[6:3], HA1)—Bits 23–20,18
DSP56367
Serial Host Interface Programming Model
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C master device initiates an
Serial Host Interface
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C slave mode
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C protocol
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