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Serial Host Interface
SHI Programming Considerations
•
MOSI/HA0 is the MOSI serial data output.
•
SS/HA2 is the SS input. It should be kept deasserted (high) for proper operation.
•
HREQ is the Host Request input.
The external slave device can be selected either by using external logic or by activating a
GPIO pin connected to its SS pin. However, the SS input pin of the SPI master device should
be held deasserted (high) for proper operation. If the SPI master device SS pin is asserted, the
host bus error status bit (HBER) is set. If the HBIE bit is also set, the SHI issues a request to
the DSP interrupt controller to service the SHI bus error interrupt.
In the SPI master mode the DSP must write to HTX to receive, transmit or perform a
full-duplex data transfer. Actually, the interface performs simultaneous data receive and
transmit. The status bits of both receive and transmit paths are active; however, the
programmer may disable undesired interrupts and ignore irrelevant status bits. In a data
transfer, the HTX is transferred to IOSR, clock pulses are generated, the IOSR data is shifted
out (via MOSI) and received data is shifted in (via MISO). The DSP programmer may write
HTX (if the HTDE status bit is set) with either DSP instructions or DMA transfers to initiate
the transfer of the next word. The HRX FIFO contains valid receive data, which the DSP can
read with either DSP instructions or DMA transfers, if the HRNE status bit is set.
It is recommended that an SHI individual reset (HEN cleared) be generated before beginning
data reception in order to reset the receive FIFO to its initial (empty) state (e.g., when
switching from transmit to receive data).
The HREQ input pin is ignored by the SPI master device if the HRQE[1:0] bits are cleared,
and considered if any of them is set. When asserted by the slave device, HREQ indicates that
the external slave device is ready for the next data transfer. As a result, the SPI master sends
clock pulses for the full data word transfer. HREQ is deasserted by the external slave device at
the first clock pulse of the new data transfer. When deasserted, HREQ prevents the clock
generation of the next data word transfer until it is asserted again. Connecting the HREQ line
between two SHI-equipped DSPs, one operating as an SPI master device and the other as an
SPI slave device, enables full hardware handshaking if CPHA = 1. For CPHA = 0, HREQ
should be disabled by clearing HRQE[1:0].
2
9.7.3
I
C SLAVE MODE
2
The I
C slave mode is entered by enabling the SHI (HEN=1), selecting the I
2
(HI
C=1), and selecting the slave mode of operation (HMST=0). In this operational mode the
contents of HCKR are ignored. When configured in the I
operate as follows:
9-24
2
C slave mode, the SHI external pins
DSP56367
2
C mode
MOTOROLA
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