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core, see Section 1 DSP56300 Core Functional Blocks on page 1-5. Significant
architectural enhancements to the DSP56300 core family include a barrel shifter, 24-bit
addressing, an instruction cache, and direct memory access (DMA).
The DSP56300 core family members contain the DSP56300 core and additional modules. The
modules are chosen from a library of standard predesigned elements such as memories and
peripherals. New modules may be added to the library to meet customer specifications. A
standard interface between the DSP56300 core and the on-chip memory and peripherals
supports a wide variety of memory and peripheral configurations. Refer to Section 5 -
Memory Configuration.
Core features are described fully in the DSP56300 Family Manual. Pinout, memory, and
peripheral features are described in this manual.
•
DSP56300 modular chassis
– 150 Million Instructions Per Second (MIPS) with a 150 MHz clock at internal
logic supply (QVCCL) of 1.8V.
–
100 Million Instructions Per Second (MIPS) with a 100 MHz clock at internal logic supply
(QVCCL) of 1.5V.
– Object Code Compatible with the 56K core.
– Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter.
16-bit arithmetic support.
– Program Control with position independent code support and instruction cache
support.
– Six-channel DMA controller.
– PLL based clocking with a wide range of frequency multiplications (1 to 4096),
predivider factors (1 to 16) and power saving clock divider (2
clock noise.
– Internal address tracing support and OnCE™ for Hardware/Software debugging.
– JTAG port.
– Very low-power CMOS design, fully static design with operating frequencies
down to DC.
– STOP and WAIT low-power standby modes.
•
On-chip Memory Configuration
– 7Kx24 Bit Y-Data RAM and 8Kx24 Bit Y-Data ROM.
– 13Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM.
MOTOROLA
DSP56367
DSP56367 Overview
DSP56300 Core Description
i
: i=0 to 7). Reduces
1-3
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