Shi Clock Generator - Motorola DSP56367 User Manual

Serial Host Interface

SHI Clock Generator

Clock control logic allows a selection of clock polarity and a choice of two fundamentally
different clocking protocols to accommodate most available synchronous serial peripheral
devices. When the SPI is configured as a master, the control bits in the HCKR select the
appropriate clock rate, as well as the desired clock polarity and phase format (see Figure 9-6).
The SS line allows selection of an individual slave SPI device; slave devices that are not
selected do not interfere with SPI bus activity (i.e., they keep their MISO output pin in the
high-impedance state). When the SHI is configured as an SPI master device, the SS line
should be held high. If the SS line is driven low when the SHI is in SPI master mode, a bus
error is generated (the HCSR HBER bit is set).
9.4 SHI CLOCK GENERATOR
The SHI clock generator generates the SHI serial clock if the interface operates in the master
mode. The clock generator is disabled if the interface operates in the slave mode, except in
2
I C mode when the HCKFR bit is set in the HCKR register. When the SHI operates in the
slave mode, the clock is external and is input to the SHI (HMST = 0). Figure 9-2 illustrates the
internal clock path connections. It is the user's responsibility to select the proper clock rate
within the range as defined in the I
SCK/SCL
Divide
By 2
F
Divide By 256
OSC
HDM0–HDM7
9.5 SERIAL HOST INTERFACE PROGRAMMING MODEL
The Serial Host Interface programming model has two parts:
• Host side—see Figure 9-3 below and Section 9.5.1
9-4
2
C and SPI bus specifications.
Divide By 1
Divide By
To
1 or 8
HRS
Figure 9-2 SHI Clock Generator
DSP56367
HMST
SHI Clock
HMST = 0
Clock
Logic
HMST = 1
CPHA, CPOL, HI
SHI
Controller
2
C
AA0417
MOTOROLA