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2
9.7.4
I
C MASTER MODE
2
The I
C master mode is entered by enabling the SHI (HEN=1), selecting the I
2
(HI
C=1) and selecting the master mode of operation (HMST=1). Before enabling the SHI as
2
an I
C master, the programmer should program the appropriate clock rate in HCKR.
When configured in the I
•
SCK/SCL is the SCL open drain serial clock output.
•
MISO/SDA is the SDA open drain serial data line.
•
MOSI/HA0 is the HA0 slave device address input.
•
SS/HA2 is the HA2 slave device address input.
•
HREQ is the Host Request input.
2
In the I
C master mode, a data transfer session is always initiated by the DSP by writing to the
HTX register when HIDLE is set. This condition ensures that the data byte written to HTX is
interpreted as being a slave address byte. This data byte must specify the slave device address
to be selected and the requested data transfer direction.
Note:
The slave address byte should be located in the high portion of the data word,
whereas the middle and low portions are ignored. Only one byte (the slave address
byte) is shifted out, independent of the word length defined by the HM[1:0] bits.
In order for the DSP to initiate a data transfer the following actions are to be performed:
•
The DSP tests the HIDLE status bit.
•
If the HIDLE status bit is set, the DSP writes the slave device address and the R/W bit
to the most significant byte of HTX.
•
The SHI generates a start event.
•
The SHI transmits one byte only, internally samples the R/W direction bit (last bit),
and accordingly initiates a receive or transmit session.
•
The SHI inspects the SDA level at the ninth clock pulse to determine the ACK value.
If acknowledged (ACK = 0), it starts its receive or transmit session according to the
sampled R/W value. If not acknowledged (ACK = 1), the HBER status bit in HCSR is
set, which causes an SHI Bus Error interrupt request if HBIE is set, and a stop event is
generated.
The HREQ input pin is ignored by the I
considered if either of them is set. When asserted, HREQ indicates that the external slave
device is ready for the next data transfer. As a result, the I
MOTOROLA
2
C master mode, the SHI external pins operate as follows:
2
C master device if HRQE[1:0] are cleared, and
DSP56367
Serial Host Interface
SHI Programming Considerations
2
C mode
2
C master device sends clock pulses
9-27
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