External Memory Support - Motorola DSP56367 User Manual

Memory Configuration
Data and Program Memory Maps
Any sequence that complies with the switch condition is valid. For example, if the program
flow executes in the address range that is not affected by the switch, the switch condition can
be met very easily. In this case a switch can be accomplished by just changing the MS, MSW0
or MSW1 bits in OMR in the regular program flow, assuming no accesses to the affected
address ranges of the data memory occur up to 3 instructions after the instruction that changes
the OMR bit. Special care should be taken in relation to the interrupt vector routines since an
interrupt could cause the DSP to fetch instructions out of sequence and might violate the
switch condition.
Special attention should be given when running a memory switch routine using the OnCE™
port. Running the switch routine in Trace mode, for example, can cause the switch to
complete after the MS bit change while the DSP is in Debug mode. As a result, subsequent
instructions might be fetched according to the new memory configuration (after the switch),
and thus might execute improperly.
5.1.5

EXTERNAL MEMORY SUPPORT

The DSP56367 does not support the SSRAM memory type. It does support SRAM and
DRAM as indicated in the DSP56300 24-Bit Digital Signal Processor Family Manual,
Motorola publication DSP56300FM/AD. Also, care should be taken when accessing external
memory to ensure that the necessary address lines are available. For example, when using
18
glueless SRAM interfacing, it is possible to directly address 3 x 2 memory locations (768k)
when using the 18 address lines and the three programmable address attribute lines.
MOTOROLA DSP56367 5-13