Motorola DSP56367 User Manual page 90

Specifications
External Memory Expansion Port (Port A)
Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Apps)
No. Characteristics
147 Last WR assertion to RAS deassertion
148 WR assertion to CAS deassertion
149 Data valid to CAS assertion (Write)
150 CAS assertion to data not valid (write)
151 WR assertion to CAS assertion
152 Last RD assertion to RAS deassertion
153 RD assertion to data valid
154
RD deassertion to data not valid
155 WR assertion to data active
156 WR deassertion to data high
impedance
Note: 1. The number of wait states for Page mode access is specified in the DCR.
2. The refresh period is specified in the DCR.
3. All the timings are calculated for the worst case. Some of the timings are better for specific cases
equals 2 × T
(e.g., t
PC
4. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be
inserted in each DRAM out-of-page access.
5. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
and not t
GZ
6. Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state see Figure 3-11.
Table 3-10 DRAM Page Mode Timings, Two Wait States
No. Characteristics
131 Page mode cycle time for two
consecutive accesses of the
same direction
Page mode cycle time for
mixed (read and write)
accesses
3-24
Symbol
t
RWL
t
CWL
t
DS
t
DH
t
WCS
t
ROH
t
GA
5 t
GZ
for read-after-read or write-after-write sequences).
C
.
Symbol
t
PC
DSP56367
20 MHz
Expression
Min
1.75 × T − 4.3
83.2
C
1.75 × T − 4.3
83.2
C
0.25 × T − 4.0
8.5
C
0.75 × T − 4.0
33.5
C
− 4.3
T 45.7
C
1.5 × T − 4.0
71.0
C
− 7.5
T —
C
0.0
0.75 × T − 0.3
37.2
C
0.25 × T
—
C
66 MHz
Expression
Min
2 × T
45.4
C
1.25 × T
41.1
C
6 6
30 MHz
Unit
Max Min Max
— 54.0 —
— 54.0 —
— 4.3 —
— 21.0 —
— 29.0 —
— 46.0 —
42.5 — 25.8
— 0.0 —
— 24.7 —
12.5 — 8.3
OFF
80 MHz
Unit
Max Min Max
— 37.5 —
— 34.4 —
MOTOROLA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns