Motorola DSP56367 User Manual page 314

Enhanced Serial Audio Interface 1 (ESAI_1)
ESAI_1 Programming Model
RHCKD=1
F
OSC
FLAG0 OUT
(SYNC MODE)
SCKR_1
SYN=0
RCKD
SCKT_1
TCKD
F
OSC
THCKD=1
Figure 11-4 ESAI_1 Clock Generator Functional Block Diagram
11-8
PRESCALE
DIVIDE BY 1
DIVIDE
OR
BY 2
DIVIDE BY 8
RPSR
FLAG0 IN
(SYNC MODE)
SYN=1
INTERNAL BIT CLOCK
TPSR
PRESCALE
DIVIDE BY 1
DIVIDE
OR
BY 2
DIVIDE BY 8
DSP56367
DIVIDER
DIVIDE BY 1
TO DIVIDE BY
256
RPM0 - RPM7
INTERNAL BIT CLOCK
RSWS4-RSWS0
RX WORD
LENGTH DIVIDER
SYN=0
RX SHIFT REGISTER
RCLOCK
TSWS4-TSWS0
SYN=1
TCLOCK
TX WORD
LENGTH DIVIDER
TX SHIFT REGISTER
TPM0 - TPM7
DIVIDER
DIVIDE BY 1
TO DIVIDE BY
256
Notes:
1. F is the DSP56300 Core internal clock frequency.
OSC
DIVIDER
DIVIDE BY 1
TO DIVIDE BY
16
RFP0 - RFP3
RX WORD
CLOCK
TX WORD
CLOCK
TFP0 - TFP3
DIVIDER
DIVIDE BY 1
TO DIVIDE BY
16
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