Shift Direction Selection - Motorola DSP56367 User Manual

Enhanced Serial Audio Interface (ESAI)
Operating Modes
The relative timing of the word length frame sync as referred to the data word is specified by
the TFSR bit in the TCR register for the transmitter section, and by the RFSR bit in the RCR
register for the receive section. The word length frame sync may be generated (or expected)
with the first bit of the data word, or with the last bit of the previous word. TFSR and RFSR
are ignored when a bit length frame sync is selected.
Polarity of the frame sync signal may be defined as positive (asserted high) or negative
(asserted low). The TFSP bit in the TCCR register specifies the polarity of the frame sync for
the transmitter section. The RFSP bit in the RCCR register specifies the polarity of the frame
sync for the receiver section.
The ESAI receiver looks for a receive frame sync leading edge (trailing edge if RFSP is set)
only when the previous frame is completed. If the frame sync goes high before the frame is
completed (or before the last bit of the frame is received in the case of a bit frame sync or a
word length frame sync with RFSR set), the current frame sync is not recognized, and the
receiver is internally disabled until the next frame sync. Frames do not have to be adjacent –
i.e., a new frame sync does not have to immediately follow the previous frame. Gaps of
arbitrary periods can occur between frames. Enabled transmitters are tri-stated during these
gaps.
When operating in the synchronous mode (SYN=1), all clocks including the frame sync are
generated by the transmitter section.
10.4.4.4

Shift Direction Selection

Some data formats, such as those used by codecs, specify MSB first while other data formats,
such as the AES-EBU digital audio interface, specify LSB first. The MSB/LSB first selection
is made by programming RSHFD bit in the RCR register for the receiver section, and by
programming the TSHFD bit in the TCR register for the transmitter section.
10.4.5 SERIAL I/O FLAGS
Three ESAI pins (FSR, SCKR and HCKR) are available as serial I/O flags when the ESAI is
operating in the synchronous mode (SYN=1). Their operation is controlled by RCKD, RFSD,
TEBE bits in the RCR, RCCR and SAICR registers.The output data bits (OF2, OF1 and OF0)
and the input data bits (IF2, IF1 and IF0) are double buffered to/from the HCKR, FSR and
SCKR pins. Double buffering the flags keeps them in sync with the TX and RX data lines.
Each flag can be separately programmed. Flag 0 (SCKR pin) direction is selected by RCKD,
RCKD=1 for output and RCKD=0 for input. Flag 1 (FSR pin) is enabled when the pin is not
configured as external transmitter buffer enable (TEBE=0) and its direction is selected by
RFSD, RFSD=1 for output and RFSD=0 for input. Flag 2 (HCKR pin) direction is selected by
RHCKD, RHCKD=1 for output and RHCKD=0 for input.
10-52 DSP56367 MOTOROLA