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DSP56367 Overview
Peripheral Overview
1.5.1
HOST INTERFACE (HDI08)
The host interface (HDI08) is a byte-wide, full-duplex, double-buffered, parallel port that can
be connected directly to the data bus of a host processor. The HDI08 supports a variety of
buses and provides glueless connection with a number of industry-standard DSPs,
microcomputers, microprocessors, and DMA hardware.
The DSP core treats the HDI08 as a memory-mapped peripheral, using either standard polled
or interrupt programming techniques. Separate transmit and receive data registers are
double-buffered to allow the DSP and host processor to efficiently transfer data at high speed.
Memory mapping allows DSP core communication with the HDI08 registers to be
accomplished using standard instructions and addressing modes.
Since the host bus may operate asynchronously with the DSP core clock, the HDI08 registers
are divided into 2 banks. The "host side" bank is accessible to the external host, and the "DSP
side" bank is accessible to the DSP core.
The HDI08 supports the following three classes of interfaces:
•
Host processor/MCU connection
•
DMA controller
•
GPIO port
Host port pins not in use may be configured as GPIO pins. The host interface provides up to
16 GPIO pins. These pins can be programmed to function as either GPIO or host interface.
For more information on the HDI08, see Section 8 - Host Interface (HDI08).
1.5.2
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
The GPIO port consists of as many as 37 programmable signals, all of which are also used by
the peripherals (HDI08, ESAI, ESAI_1, DAX, and TEC). There are no dedicated GPIO
signals. The signals are configured as GPIO after hardware reset. Register programming
techniques for all GPIO functionality among these interfaces are very similar.
1-12
DSP56367
MOTOROLA
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