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Digital Audio Transmitter
GPIO (PORT D) - Pins and Registers
12.7.1
PORT D CONTROL REGISTER (PCRD)
The read/write 24-bit DAX Port D Control Register controls the functionality of the DAX
GPIO pins. Each of the PC[1:0] bits controls the functionality of the corresponding port pin.
When a PC[i] bit is set, the corresponding port pin is configured as a DAX pin. When a PC[i]
bit is cleared, the corresponding port pin is configured as GPIO pin. If both PC1 and PC0 are
cleared, the DAX is disabled. Hardware and software reset clear all PCRD bits.
PCRD -Port D Control Register - X:$FFFFD7
23
22
21
20
19
read as zero, should be written with zero for future compatibility
Figure 12-7 Port D Control Register (PCRD)
12.7.2
PORT D DIRECTION REGISTER (PRRD)
The read/write 24-bit Port D Direction Register controls the direction of the DAX GPIO pins.
When port pin[i] is configured as GPIO, PDC[i] controls the port pin direction. When PDC[i]
is set, the GPIO port pin[i] is configured as output. When PDC[i] is cleared the GPIO port
pin[i] is configured as input. Hardware and software reset clear all PRRD bits. Table 12-6
describes the port pin configurations.
PRRD - Port D Direction Register - X:$FFFFD6
23
22
21
20
19
read as zero, should be written with zero for future compatibility
Figure 12-8 Port D Direction Register (PRRD)
12-16
18
17
16
15
14
13
18
17
16
15
14
13
12
DSP56367
12
11
10
9
8
7
6
11
10
9
8
7
6
5
4
3
2
1
0
PC1
PC0
5
4
3
2
1
0
PDC1
PDC0
MOTOROLA
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