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•
HREQ is the Host Request output.
In the SPI slave mode, a receive, transmit, or full-duplex data transfer may be performed.
Actually, the interface performs data receive and transmit simultaneously. The status bits of
both receive and transmit paths are active; however, the programmer may disable undesired
interrupts and ignore irrelevant status bits. It is recommended that an SHI individual reset
(HEN cleared) be generated before beginning data reception in order to reset the HRX FIFO
to its initial (empty) state (e.g., when switching from transmit to receive data).
If a write to HTX occurs, its contents are transferred to IOSR between data word transfers.
The IOSR data is shifted out (via MISO) and received data is shifted in (via MOSI). The DSP
may write HTX with either DSP instructions or DMA transfers if the HTDE status bit is set. If
no writes to HTX occur, the contents of HTX are not transferred to IOSR, so the data shifted
out when receiving is the data present in the IOSR at the time. The HRX FIFO contains valid
receive data, which the DSP can read with either DSP instructions or DMA transfers (if the
HRNE status bit is set).
The HREQ output pin, if enabled for receive (HRQE[1:0] = 01), is asserted when the IOSR is
ready for receive and the HRX FIFO is not full; this operation guarantees that the next
received data word is stored in the FIFO. The HREQ output pin, if enabled for transmit
(HRQE[1:0] = 10), is asserted when the IOSR is loaded from HTX with a new data word to
transfer. If HREQ is enabled for both transmit and receive (HRQE[1:0] = 11), it is asserted
when the receive and transmit conditions are both true. HREQ is deasserted at the first clock
pulse of the next data word transfer. The HREQ line may be used to interrupt the external
master device. Connecting the HREQ line between two SHI-equipped DSPs, one operating as
an SPI master device and the other as an SPI slave device, enables full hardware handshaking
if operating with CPHA = 1.
The SS line should be kept asserted during a data word transfer. If the SS line is deasserted
before the end of the data word transfer, the transfer is aborted and the received data word is
lost.
9.7.2
SPI MASTER MODE
The SPI master mode is initiated by enabling the SHI (HEN = 1), selecting the SPI mode
2
(HI
C = 0), and selecting the master mode of operation (HMST = 1). Before enabling the SHI
as an SPI master device, the programmer should program the proper clock rate, phase and
polarity in HCKR. When configured in the SPI master mode, the SHI external pins operate as
follows:
•
SCK/SCL is the SCK serial clock output.
•
MISO/SDA is the MISO serial data input.
MOTOROLA
SHI Programming Considerations
DSP56367
Serial Host Interface
9-23
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