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When the SHI is in slave mode and CPHA = 0, the SS line must be deasserted and asserted by
the external master between each successive word transfer. SS must remain asserted between
successive bytes within a word. The DSP core should write the next data word to HTX when
HTDE = 1, clearing HTDE. However, the data is transferred to the shift register for
transmission only when SS is deasserted. HTDE is set when the data is transferred from HTX
to the shift register.
When the SHI is in slave mode and CPHA = 1, the SS line may remain asserted between
successive word transfers. The SS must remain asserted between successive bytes within a
word. The DSP core should write the next data word to HTX when HTDE = 1, clearing
HTDE. The HTX data is transferred to the shift register for transmission as soon as the shift
register is empty. HTDE is set when the data is transferred from HTX to the shift register.
When the SHI is in master mode and CPHA = 0, the DSP core should write the next data word
to HTX when HTDE = 1, clearing HTDE. The data is transferred immediately to the shift
register for transmission. HTDE is set only at the end of the data word transmission.
Note:
The master is responsible for deasserting and asserting the slave device SS line
between word transmissions.
When the SHI is in master mode and CPHA = 1, the DSP core should write the next data word
to HTX when HTDE = 1, clearing HTDE. The HTX data is transferred to the shift register for
transmission as soon as the shift register is empty. HTDE is set when the data is transferred
from HTX to the shift register.
9.5.5.2
HCKR Prescaler Rate Select (HRS)—Bit 2
The HRS bit controls a prescaler in series with the clock generator divider. This bit is used to
extend the range of the divider when slower clock rates are desired. When HRS is set, the
prescaler is bypassed. When HRS is cleared, the fixed divide-by-eight prescaler is operational.
HRS is ignored when the SHI operates in the slave mode, except for I
The HRS bit is cleared during hardware reset and software reset.
Note:
Use the equations in the SHI datasheet to determine the value of HRS for the
specific serial clock frequency required.
9.5.5.3
HCKR Divider Modulus Select (HDM[7:0])—Bits 10–3
The HDM[7:0] bits specify the divide ratio of the clock generator divider. A divide ratio
between 1 and 256 (HDM[7:0] = $00 to $FF) may be selected. When the SHI operates in the
slave mode, the HDM[7:0] bits are ignored (except for I
HDM[7:0] bits are cleared during hardware reset and software reset.
Note:
Use the equations in the SHI datasheet to determine the value of HDM[7:0] for the
specific serial clock frequency required.
MOTOROLA
Serial Host Interface Programming Model
2
C when HCKFR is set). The
DSP56367
Serial Host Interface
2
C when HCKFR is set.
9-11
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