Prescaler Counter - Motorola DSP56367 User Manual

13.3.1

PRESCALER COUNTER

The prescaler counter is a 21-bit counter that is decremented on the rising edge of the
prescaler input clock. The counter is enabled when at least one of the three timers is enabled
(i.e., one or more of the timer enable (TE) bits are set) and is using the prescaler output as its
source (i.e., one or more of the PCE bits are set).
13.3.2 TIMER PRESCALER LOAD REGISTER (TPLR)
The TPLR is a 24-bit read/write register that controls the prescaler divide factor (i.e., the
number that the prescaler counter will load and begin counting from) and the source for the
prescaler input clock. See Figure 13-4.
23 22 21
PS1 PS0
11 10 9
PL11 PL10 PL9
— reserved, read as 0, should be written with 0 for future compatibility
Figure 13-4 Timer Prescaler Load Register (TPLR)
13.3.2.1 TPLR Prescaler Preload Value PL[20:0] Bits 20–0
These 21 bits contain the prescaler preload value. This value is loaded into the prescaler
counter when the counter value reaches zero or the counter switches state from disabled to
enabled.
If PL[20:0] = N, then the prescaler counts N + 1 source clock cycles before generating a
prescaler clock pulse. Therefore, the prescaler divide factor = (preload value) + 1.
The PL[20:0] bits are cleared by the hardware RESET signal or the software RESET
instruction.
13.3.2.2 TPLR Prescaler Source PS[1:0] Bits 22-21
The two prescaler source (PS) bits control the source of the prescaler clock. Table 13-1
summarizes PS bit functionality. The prescaler's use of the TIO0 signal is not affected by the
TCSR settings of timer 0.
If the prescaler source clock is external, the prescaler counter is incremented by signal
transitions on the TIO0 signal. The external clock is internally synchronized to the internal
clock. The external clock frequency must be lower than the DSP56367 internal operating
frequency divided by 4 (CLK/4).
MOTOROLA
19 18
20
PL20 PL19 PL18
8 7 6
PL8 PL7 PL6
DSP56367
Timer/Event Counter Programming Model
17 16 15
PL17 PL16 PL15
5 4 3
PL5 PL4 PL3
Timer/ Event Counter
14 13 12
PL14 PL13 PL12
2 1 0
PL2 PL1 PL0
13-5