Motorola DSP56367 User Manual page 92

Specifications
External Memory Expansion Port (Port A)
Table 3-10 DRAM Page Mode Timings, Two Wait States (Continued)
No. Characteristics
145 CAS assertion to WR
deassertion
146 WR assertion pulse width
147 Last WR assertion to RAS
deassertion
148 WR assertion to CAS
deassertion
149 Data valid to CAS assertion
(write)
150 CAS assertion to data not valid
(write)
151 WR assertion to CAS assertion
152 Last RD assertion to RAS
deassertion
153 RD assertion to data valid
154 RD deassertion to data not
6
valid
155 WR assertion to data active
156 WR deassertion to data high
impedance
Note: 1. The number of wait states for Page mode access is specified in the DCR.
2. The refresh period is specified in the DCR.
3. The asynchronous delays specified in the expressions are valid for DSP56367.
4. All the timings are calculated for the worst case. Some of the timings are better for specific
cases (e.g., t
5. BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be
inserted in each DRAM out-of-page access.
6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
and not t
GZ.
7. There are no DRAMs fast enough to fit to two wait states Page mode @ 100MHz (See
Figure 3-11)
3-26
Symbol
1.5 × T
t
WCH
2.5 × T
t
WP
2.75 × T
t
RWL
2.5 × T
t
CWL
0.25 × T
t
DS
0.25 × T
1.75 × T
t
DH
t
WCS
2.5 × T
t
ROH
1.75 × T
t
GA
1.75 × T
t
GZ
0.75 × T
equals 3 × T
for read-after-read or write-after-write sequences).
PC C
DSP56367
66 MHz
Expression
Min
− 4.2
18.5
C
− 4.5
33.5
C
− 4.3
33.4
C
− 4.3
33.6
C
− 3.7
0.1
C
− 3.0
—
C
− 4.0
22.5
C
− 4.3
T 10.9
C
− 4.0
33.9
C
− 7.5
—
C
− 6.5
—
C
0.0
− 0.3
11.1
C
0.25 × T
—
C
80 MHz
Unit
Max Min Max
— 14.6 —
— 26.8 —
— 26.8 —
— 27.0 —
— — —
— 0.1 —
— 17.9 —
— 8.2 —
— 27.3 —
19.0 — —
— — 15.4
— 0.0 —
— 9.1 —
3.8 — 3.1
OFF
MOTOROLA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns