Clock And Pll - Motorola DSP56367 User Manual

Ground Name
GND (4) Address Bus Ground—GND
A
must be tied externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors. There are four GND
GND (4) Data Bus Ground—GND
D
tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.
There are four GND
GND (2) Bus Control Ground—GND
C
externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.
There are two GND
GND Host Ground—GND
H
other chip ground connections. The user must provide adequate external decoupling capacitors. There is one GND
connection.
GND (2) SHI, ESAI, ESAI_1, DAX and Timer Ground—GND
S
and Timer. This connection must be tied externally to all other chip ground connections. The user must provide
adequate external decoupling capacitors. There are two GND
2.4

CLOCK AND PLL

Signal Name Type
EXTAL Input
PCAP Input
PINIT/NMI Input
MOTOROLA
Table 2-3 Grounds
is an isolated ground for sections of the address bus I/O drivers. This connection
A
connections.
A
is an isolated ground for sections of the data bus I/O drivers. This connection must be
D
connections.
D
is an isolated ground for the bus control I/O drivers. This connection must be tied
C
connections.
C
is an isolated ground for the HD08 I/O drivers. This connection must be tied externally to all
h
Table 2-4 Clock and PLL Signals
State
during
Reset
Input External Clock Input—An external clock source must be connected to EXTAL in
order to supply the clock to the internal clock generator and PLL.
Input PLL Capacitor—PCAP is an input connecting an off-chip capacitor to the PLL filter.
Connect one capacitor terminal to PCAP and the other terminal to V
If the PLL is not used, PCAP may be tied to V
Input PLL Initial/Nonmaskable Interrupt—During assertion of RESET, the value of
PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,
determining whether the PLL is enabled or disabled. After RESET de assertion and
during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a
negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized
to internal system clock.
DSP56367
Signal/Connection Descriptions
Description
is an isolated ground for the SHI, ESAI, ESAI_1, DAX
S
connections.
S
Signal Description
, GND, or left floating.
CC
Clock and PLL
H
.
CCP
2-5