Motorola DSP56367 User Manual page 51

Table 2-7 External Bus Control Signals (Continued)
Signal
Type
Name
CAS Output
RD Output
WR Output
TA Input
BR Output
(deasserted)
BG Input
MOTOROLA
State
during
Reset
Tri-stated Column Address Strobe— When the DSP is the bus master, CAS is an active-low output
used by DRAM to strobe the column address. Otherwise, if the bus mastership enable
(BME) bit in the DRAM control register is cleared, the signal is tri-stated.
Tri-stated Read Enable—When the DSP is the bus master, RD is an active-low output that is
asserted to read external memory on the data bus (D0-D23). Otherwise, RD is tri-stated.
Tri-stated Write Enable—When the DSP is the bus master, WR is an active-low output that is
asserted to write external memory on the data bus (D0-D23). Otherwise, WR is tri-stated.
Ignored Transfer Acknowledge—If the DSP is the bus master and there is no external bus
Input activity, or the DSP is not the bus master, the TA input is ignored. The TA input is a data
transfer acknowledge (DTACK) function that can extend an external bus cycle
indefinitely. Any number of wait states (1, 2. . .infinity) may be added to the wait states
inserted by the BCR by keeping TA deasserted. In typical operation, TA is deasserted at
the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted
before the next bus cycle. The current bus cycle completes one clock period after TA is
asserted synchronous to the internal system clock. The number of wait states is
determined by the TA input or by the bus control register (BCR), whichever is longer. The
BCR can be used to set the minimum number of wait states in external bus cycles.
In order to use the TA functionality, the BCR must be programmed to at least one wait
state. A zero wait state access cannot be extended by TA deassertion, otherwise improper
operation may result. TA can operate synchronously or asynchronously, depending on the
setting of the TAS bit in the operating mode register (OMR).
TA functionality may not be used while performing DRAM type accesses, otherwise
improper operation may result.
Output Bus Request—BR is an active-low output, never tri-stated. BR is asserted when the DSP
requests bus mastership. BR is deasserted when the DSP no longer needs the bus. BR may
be asserted or deasserted independent of whether the DSP56367 is a bus master or a bus
slave. Bus "parking" allows BR to be deasserted even though the DSP56367 is the bus
master. (See the description of bus "parking" in the BB signal description.) The bus
request hold (BRH) bit in the BCR allows BR to be asserted under software control even
though the DSP does not need the bus. BR is typically sent to an external bus arbitrator
that controls the priority, parking, and tenure of each master on the same external bus. BR
is only affected by DSP requests for the external bus, never for the internal bus. During
hardware reset, BR is deasserted and the arbitration is reset to the bus slave state.
Ignored Bus Grant—BG is an active-low input. BG is asserted by an external bus arbitration
Input circuit when the DSP56367 becomes the next bus master. When BG is asserted, the
DSP56367 must wait until BB is deasserted before taking bus mastership. When BG is
deasserted, bus mastership is typically given up at the end of the current bus cycle. This
may occur in the middle of an instruction that requires more than one external bus cycle
for execution.
For proper BG operation, the asynchronous bus arbitration enable bit (ABE) in the OMR
register must be set.
DSP56367
Signal/Connection Descriptions
External Memory Expansion Port (Port A)
Signal Description
2-7