Audio Data Register Empty Interrupt Enable (Xdie)—Bit 0 - Motorola DSP56367 User Manual

Digital Audio Transmitter
DAX Internal Architecture
12.5.6.1 Audio Data Register Empty Interrupt Enable (XDIE)—Bit 0
When the XDIE bit is set, the audio data register empty interrupt is enabled and sends an
interrupt request signal to the DSP if the XADE status bit is set. When XDIE bit is cleared,
this interrupt is disabled.
12.5.6.2 Underrun Error Interrupt Enable (XUIE)—Bit 1
When the XUIE bit is set, the underrun error interrupt is enabled and sends an interrupt
request signal to the DSP if the XAUR status bit is set. When XUIE bit is cleared, this
interrupt is disabled.
12.5.6.3 Block Transferred Interrupt Enable (XBIE)—Bit 2
When the XBIE bit is set, the block transferred interrupt is enabled and sends an interrupt
request signal to the DSP if the XBLK and XADE status bits are set. When XBIE bit is
cleared, this interrupt is disabled.
12.5.6.4 DAX Clock Input Select (XCS[1:0])—Bits 3–4
The XCS[1:0] bits select the source of the DAX clock and/or its frequency. Table 12-3 shows
the configurations selected by these bits. These bits should be changed only when the DAX is
disabled.
XCS1
12.5.6.5 DAX Start Block (XSB)—Bit 5
The XSB bit forces the DAX to start a new block. When this bit is set, the next frame will start
with "Z" preamble and will start a new block even though the current block was not finished.
This bit is cleared when the new block starts.
12.5.6.6 XCTR Reserved Bits—Bits 6-23
These XCTR bits are reserved. They read as 0 and should be written with 0 for future
compatibility.
12-8
Table 12-3 Clock Source Selection
XCS0
0 0
0 1
1 0
1 1
DSP56367
DAX Clock Source
x
DSP Core Clock (f = 1024 fs)
x
ACI Pin, f = 256 fs
x
ACI Pin, f = 384 fs
x
ACI Pin, f = 512 fs
MOTOROLA