Motorola DSP56367 User Manual page 28

SECTION 4—DESIGN CONSIDERATIONS
– Describes thermal, electrical, and power consumption issues, as wells PLL
performance issues and input jitter requirements for the DSP56367.
SECTION 5—MEMORY CONFIGURATION
– Describes data and program and memory maps for the DSP56367.
SECTION 6—CORE CONFIGURATION
– Describes the registers used to configure the DSP56300 core when programming the
DSP56367, in particular the interrupt vector locations and the operation of the
interrupt priority registers. Explains the operating modes and how they affect the
processor's program and data memories.
SECTION 7—GENERAL PURPOSE INPUT/OUTPUT (GPIO)
– Describes the DSP56367 GPIO capability and the programming model for the GPIO
signals (operation, registers, and control).
SECTION 8— HOST INTERFACE (HDI08)
– Describes the HDI08 parallel host interface.
SECTION 9—SERIAL HOST INTERFACE (SHI)
– Describes the serial input/output interface providing a path for communication and
program/coefficient data transfers between the DSP and an external host processor.
The SHI can also communicate with other serial peripheral devices.
SECTION 10—ENHANCED SERIAL AUDIO INTERFACE (ESAI)
– Describes one of the full-duplex serial port for serial communication with a variety of
serial devices.
SECTION 11—ENHANCED SERIAL AUDIO INTERFACE 1 (ESAI_1)
– Describes the second full-duplex serial port for serial communication with a variety of
serial devices.
SECTION 12—DIGITAL AUDIO TRANSMITTER (DAX)
– Describes the full-duplex serial port for serial communication with a variety of serial
devices.
SECTION 13—TRIPLE TIMER MODULE (TEC)
– Describes the internal timer/event counter in the DSP56367.
SECTION 14—PACKAGE DESCRIPTION
– Describes the available package for the DSP56367, including diagrams of the package
pinouts and tables describing how the signals are allocated for the package.
APPENDIX A—BOOTSTRAP PROGRAM
– Lists the bootstrap code used for the DSP56367.
APPENDIX B—EQUATES
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