D.2 Internal I/O Memory Map - Motorola DSP56367 User Manual

Programmer's Reference
D.2 INTERNAL I/O MEMORY MAP
Peripheral Address
IPR X:$FFFFFF
X:$FFFFFE
PLL X:$FFFFFD
ONCE X:$FFFFFC
BIU X:$FFFFFB
X:$FFFFFA
X:$FFFFF9
X:$FFFFF8
X:$FFFFF7
X:$FFFFF6
X:$FFFFF5
DMA X:$FFFFF4
X:$FFFFF3
X:$FFFFF2
X:$FFFFF1
X:$FFFFF0
DMA0 X:$FFFFEF
X:$FFFFEE
X:$FFFFED
X:$FFFFEC
DMA1 X:$FFFFEB
X:$FFFFEA
X:$FFFFE9
X:$FFFFE8
DMA2 X:$FFFFE7
X:$FFFFE6
X:$FFFFE5
X:$FFFFE4
DMA3 X:$FFFFE3
X:$FFFFE2
X:$FFFFE1
X:$FFFFE0
DMA4 X:$FFFFDF
X:$FFFFDE
X:$FFFFDD
X:$FFFFDC
DMA5 X:$FFFFDB
X:$FFFFDA
X:$FFFFD9
X:$FFFFD8
PORT D X:$FFFFD7
X:$FFFFD6
X:$FFFFD5
D-2
Table D-1 Internal I/O Memory Map
INTERRUPT PRIORITY REGISTER CORE (IPR-C)
INTERRUPT PRIORITY REGISTER PERIPHERAL (IPR-P)
PLL CONTROL REGISTER (PCTL)
ONCE GDB REGISTER (OGDB)
BUS CONTROL REGISTER (BCR)
DRAM CONTROL REGISTER (DCR)
ADDRESS ATTRIBUTE REGISTER 0 (AAR0)
ADDRESS ATTRIBUTE REGISTER 1 (AAR1)
ADDRESS ATTRIBUTE REGISTER 2 (AAR2)
ADDRESS ATTRIBUTE REGISTER 3 (AAR3) [pin not available]
ID REGISTER (IDR)
DMA STATUS REGISTER (DSTR)
DMA OFFSET REGISTER 0 (DOR0)
DMA OFFSET REGISTER 1 (DOR1)
DMA OFFSET REGISTER 2 (DOR2)
DMA OFFSET REGISTER 3 (DOR3)
DMA SOURCE ADDRESS REGISTER (DSR0)
DMA DESTINATION ADDRESS REGISTER (DDR0)
DMA COUNTER (DCO0)
DMA CONTROL REGISTER (DCR0)
DMA SOURCE ADDRESS REGISTER (DSR1)
DMA DESTINATION ADDRESS REGISTER (DDR1)
DMA COUNTER (DCO1)
DMA CONTROL REGISTER (DCR1)
DMA SOURCE ADDRESS REGISTER (DSR2)
DMA DESTINATION ADDRESS REGISTER (DDR2)
DMA COUNTER (DCO2)
DMA CONTROL REGISTER (DCR2)
DMA SOURCE ADDRESS REGISTER (DSR3)
DMA DESTINATION ADDRESS REGISTER (DDR3)
DMA COUNTER (DCO3)
DMA CONTROL REGISTER (DCR3)
DMA SOURCE ADDRESS REGISTER (DSR4)
DMA DESTINATION ADDRESS REGISTER (DDR4)
DMA COUNTER (DCO4)
DMA CONTROL REGISTER (DCR4)
DMA SOURCE ADDRESS REGISTER (DSR5)
DMA DESTINATION ADDRESS REGISTER (DDR5)
DMA COUNTER (DCO5)
DMA CONTROL REGISTER (DCR5)
PORT D CONTROL REGISTER (PCRD)
PORT D DIRECTION REGISTER (PRRD)
PORT D DATA REGISTER (PDRD)
DSP56367
Register Name
MOTOROLA