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– Lists equates for the DSP56367.
APPENDIX C—JTAG/BSDL LISTING
– Provides the BSDL listing for the DSP56367.
APPENDIX D—PROGRAMMING REFERENCE
– Lists peripheral addresses, interrupt addresses, and interrupt priorities for the
DSP56367. Contains programming sheets listing the contents of the major DSP56367
registers for programmer reference.
APPENDIX E—POWER CONSUMPTION BENCHMARK
– Describes the benchmark program that permits evaluation of DSP power usage in a
test situation.
APPENDIX F—IBIS MODEL
– Describes the IBIS model used for the DSP56367.
Manual Conventions
The following conventions are used in this manual:
•
Bits within registers are always listed from most significant bit (MSB) to least significant
bit (LSB).
•
When several related bits are discussed, they are referenced as AA[n:m], where n>m. For
purposes of description, the bits are presented as if they are contiguous within a register.
However, this is not always the case. Refer to the programming model diagrams or to the
programmer's sheets to see the exact location of bits within a register.
•
When a bit is described as "set", its value is 1. When a bit is described as "cleared", its
value is 0.
•
The word "assert" means that a high true (active high) signal is pulled high to V
a low true (active low) signal is pulled low to ground. The word "deassert" means that a
high true signal is pulled low to ground or that a low true signal is pulled high to V
Signal/Symbol
PIN
PIN
PIN
PIN
MOTOROLA
High True/Low True Signal Conventions
Logic State
1
True
False
True
False
About This Guide
Signal State
Asserted
Deasserted
Asserted
Deasserted
or that
CC
.
CC
Voltage
2
Ground
3
V
CC
V
CC
Ground
iii
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