Tccr Tx High Frequency Clock Divider (Tfp3-Tfp0) - Bits 14–17 - Motorola DSP56367 User Manual

RDC0 - RDC4
RX WORD
CLOCK
RECEIVER
FRAME RATE
DIVIDER
RECEIVE
CONTROL
LOGIC
TDC0 - TDC4
TX WORD
CLOCK
TRANSMITTER
FRAME RATE
DIVIDER
TRANSMIT
CONTROL
LOGIC
Figure 10-4 ESAI Frame Sync Generator Functional Block Diagram
10.3.1.4 TCCR Tx High Frequency Clock Divider (TFP3-TFP0) - Bits 14–17
The TFP3–TFP0 bits control the divide ratio of the transmitter high frequency clock to the
transmitter serial bit clock when the source of the high frequency clock and the bit clock is the
internal DSP clock. When the HCKT input is being driven from an external high frequency
clock, the TFP3-TFP0 bits specify an additional division ratio in the clock divider chain. See
Table 10-3 for the specification of the divide ratio. The ESAI high frequency clock generator
functional diagram is shown in Figure 10-3.
MOTOROLA
RFSL
INTERNAL RX FRAME CLOCK
SYNC
TYPE
SYN=0
RECEIVE
FRAME SYNC
SYN=1
TFSL
INTERNAL TX FRAME CLOCK
SYNC
TYPE
TRANSMIT
FRAME SYNC
DSP56367
Enhanced Serial Audio Interface (ESAI)
ESAI Programming Model
SYN=0
RFSD=1
RFSD=0
SYN=1
FLAG1 IN FLAG1OUT
(SYNC MODE) (SYNC MODE)
RFSD
FSR
TFSD
FST
10-13