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SECTION
SERIAL HOST INTERFACE
9.1
INTRODUCTION
The Serial Host Interface (SHI) is a serial I/O interface that provides a path for
communication and program/coefficient data transfers between the DSP and an external host
processor. The SHI can also communicate with other serial peripheral devices. The SHI
supports two well-known and widely used synchronous serial buses: the Motorola Serial
Peripheral Interface (SPI) bus and the Philips Inter-Integrated-Circuit Control (I
SHI supports either bus protocol as either a slave or a single-master device. To minimize DSP
overhead, the SHI supports 8-bit, 16-bit and 24-bit data transfers. The SHI has a 1 or 10-word
receive FIFO that permits receiving up to 30 bytes before generating a receive interrupt,
reducing the overhead for data reception.
When configured in the SPI mode, the SHI can perform the following functions:
•
Identify its slave selection (in slave mode)
•
Simultaneously transmit (shift out) and receive (shift in) serial data
•
Directly operate with 8-, 16- and 24-bit words
•
Generate vectored interrupts separately for receive and transmit events and update
status bits
•
Generate a separate vectored interrupt for a receive exception
•
Generate a separate vectored interrupt for a bus-error exception
•
Generate the serial clock signal (in master mode)
•
Trigger DMA interrupts to service the transmit and receive events
When configured in the I
•
Detect/generate start and stop events
•
Identify its slave (ID) address (in slave mode)
•
Identify the transfer direction (receive/transmit)
•
Transfer data byte-wise according to the SCL clock line
MOTOROLA
9
2
C mode, the SHI can perform the following functions:
DSP56367
2
C) bus. The
9-1
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