Hdi08 – External Host Programmer's Model - Motorola DSP56367 User Manual

must read or write the appropriate HDI08 register (clearing HRDF or HTDE, for example) to
clear the interrupt. In the case of host command interrupts, the interrupt acknowledge from the
DSP core program controller clears the pending interrupt condition. Figure 8-11 illustrates the
HSR-HCR operation.
15
X:HCR
15
X:HSR
8.6 HDI08 – EXTERNAL HOST PROGRAMMER'S MODEL
The HDI08 has been designed to provide a simple, high speed interface to a host processor.
To the host bus, the HDI08 appears to be eight byte-wide registers. Separate transmit and
receive data registers are double-buffered to allow the DSP core and host processor to transfer
data efficiently at high speed. The host may access the HDI08 asynchronously by using
polling techniques or interrupt-based techniques.
The HDI08 appears to the host processor as a memory-mapped peripheral occupying 8 bytes
in the host processor address space (See Table 8-8). The eight HDI08 include the following:
• A control register (ICR)
• A status register (ISR)
• Three data registers (RXH/TXH, RXM/TXM and RXL/TXL)
MOTOROLA
HDI08 – External Host Programmer's Model
ENABLE
HF3 HF2 HCIE HTIE
HF1 HF0 HCP HTDE
Figure 8-11 HSR-HCR Operation
DSP56367
Host Interface (HDI08)
0
HRIE HCR
0
HRDF HSR
STATUS
DSP CORE INTERRUPTS
RECIEVE DATA FULL
TRANSMIT DATA EMPTY
HOST COMMAND
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