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2
1
DAX
TRIPLE
(SPDIF Tx.)
TIMER
INTER-FA
CE
ADDRESS
GENERATION
UNIT
SIX CHANNELS
DMA UNIT
INTERNAL
DATA
BUS
PLL
CLOCK
GENERAT
EXTAL
RESET
PINIT/NMI
1.2
DSP56300 CORE DESCRIPTION
The DSP56367 uses the DSP56300 core, a high-performance, single clock cycle per
instruction engine that provides up to twice the performance of Motorola's popular DSP56000
core family while retaining code compatibility with it.
The DSP56300 core family offers a new level of performance in speed and power, provided
by its rich instruction set and low power dissipation, thus enabling a new generation of
wireless, telecommunications, and multimedia products. For a description of the DSP56300
MOTOROLA
4
8
16
6
HOST
SHI
ESAI
INTER-
INTER-
INTER-
FACE
FACE
FACE
ESAI_1
PERIPHERAL
EXPANSION AREA
24-BIT
DSP56300
Core
PROGRAM
PROGRAM
INTERRUPT
DECODE
CONTROLLER
CONTROLLE
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Figure 1-1 DSP56367 Block Diagram
DSP56367
5
MEMORY EXPANSION AREA
X MEMORY
PROGRAM
RAM
RAM
/INSTR.
13K X 24
CACHE
ROM
3K x 24
PROGRAM
32K x 24
ROM
40K x 24
Bootstrap
YAB
XAB
PAB
DAB
DDB
YDB
XDB
PDB
GDB
DATA ALU
PROGRAM
24X24 + 56 -> 56-BIT MAC
ADDRESS
TWO 56-BIT ACCUMULATORS
GENERATOR
BARREL SHIFTER
Y MEMORY
RAM
7K X 24
ROM
8K x 24
EXTERNAL
18
ADDRESS
BUS
ADDRESS
SWITCH
DRAM &
10
SRAM BUS
INTERFACE
&
CONTROL
I - CACHE
EXTERNAL
24
DATA BUS
SWITCH
DATA
POWER
MNGMNT
4
JTAG
OnCE™
24 BITS BUS
1-2
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