Memory Space - Motorola DSP96002 User Manual

and may change only when
ware reset.
D0-D31 (Data Bus) - three-state, active high, bidirectional input/outputs when a bus master or
not a bus master. The Data Enable (
D0-D31. As a bus master, the data lines are controlled by the CPU instruction execution
or the DMA controller. D0-D31 are also the Host Interface data lines. If there is no ex-
ternal bus activity, D0-D31 are three-stated. D0-D31 are also three-stated during hard-
ware reset.
S1,S0 (Space Select) - three-state, active low outputs when a bus master, three-stated when
not a bus master. Timing is the same as the address lines A0-A31. S1 and S0 are three-
stated during hardware reset.
These signals can be viewed in different ways, depending on how the external memo-
ries are mapped. They support the trend toward splitting memory spaces among ports
and mapping multiple memory spaces into the same physical memory locations. Sev-
eral examples are given in Figure 2-3 . The encoding S1:S0=11 may be used to place
external memories in their low power standby mode.
—
R/ W (Read/Write)- three-state, active low output when a bus master, active low input when
not a bus master. Bus master timing is the same as the DSP96002 address lines, giving
EXTERNAL MEMORY AND MAPPING
P only
X only
Y only
X and Y mapped as 1 or 2 spaces
P and X mapped as 2 spaces
P and Y mapped as 1 space
P, X, and Y mapped as 1 space
Figure 2-3. Program and Data Memory Select Encoding
2 - 6
— –
T S is deasserted. A0-A31 are three-stated during hard-
—
S1 S0

MEMORY SPACE

1 1 No access
1 0 P access
0 1 X access
0 0 Y access
S1 FUNCTION
DSP96002 USER'S MANUAL
–
D E) input acts as an output enable control for
S0 FUNCTION
—
—
— –
D S —
— –
D S —
— –
D S X/
— – —
D S
— – — – — –
P S/ D S P
— – — –
P S/ D S —
–
P S
–
Y
–
P S
— –
S and D S
MOTOROLA