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On the DSP96002, the upper and lower boundaries are not explicitly needed. If the address register pointer
increments past the upper boundary of the buffer (base address plus M-1) it will wrap around to the base
address. If the address decrements past the lower boundary (base address) it will wrap around to the base
address plus M-1.
If an offset Nn is used in the address calculations, the 32-bit value Nn must be less than or equal to M for
proper modulo addressing. This is because a single modulo wrap around is detected. If Nn is greater than
k
M, the result is data dependent and unpredictable except for the special case where Nn=L*(2
), a multiple
k
of the block size, 2
, where L is a positive integer. Note that the offset Nn must be a positive two's comple-
ment integer. For this case the pointer Rn will be incremented using linear arithmetic to the same relative
address L blocks forward in memory. Similarly, for the (Rn)-Nn addressing mode the pointer Rn will be dec-
remented, using linear arithmetic, L blocks backward in memory. For the normal case where Nn is less
than or equal to M, the modulo arithmetic unit will automatically wrap the address pointer around by the
required amount. This type of address modification is useful in creating circular buffers for FIFOs (queues),
delay lines and sample buffers up to 16,777,216 words long. It is also used for decimation, interpolation,
k
and waveform generation. The special case of (Rn)+/-Nn with Nn=L*(2
) is useful for performing the same
algorithm on multiple buffers, for example implementing a bank of parallel filters. The range of values for
Nn is -2,147,483,648 to +2,147,483,647 although all values are not useful when modulo addressing as de-
scribed above.
5.8.4 Multiple Wrap-Around Modulo Modifier
1
The address modification is performed modulo M, where M may be any power of 2 in the range from 2
to
23
2
. Modulo M arithmetic causes the address register value to remain within an address range of size M
defined by a lower and upper address boundary. The value M-1 is stored in the modifier register Mn least
significant 24 bits while the 8 most significant bits are set to $FF. The lower boundary (base address) value
k
k
must have zeroes in the k LSBs, where 2
= M , and therefore must be a multiple of 2
. The upper boundary
is the lower boundary plus the modulo size minus one (base address plus M-1).
For example, to create a circular buffer of 32 stages, M is chosen as 32 and the lower address boundary
k
must have its 5 LSBs equal to zero (2
= 32, thus k = 5). The Mn register is loaded with the value
$FF00001F. The lower boundary may be chosen as 0, 32, 64, 96, 128, 160, etc. The upper boundary of
the buffer is then the lower boundary plus 31.
The address pointer is not required to start at the lower address boundary and may begin anywhere within
the defined modulo address range (between the lower and upper boundaries). If the address register
pointer increments past the upper boundary of the buffer (base address plus M-1) it will wrap around to the
base address. If the address decrements past the lower boundary (base address) it will wrap around to
the base address plus M-1. If an offset Nn is used in the address calculations, the 32-bit value Nn is not
required to be less than or equal to M for proper modulo addressing since multiple wrap around is support-
ed for (Rn)+Nn, (Rn)-Nn and (Rn+Nn) address updates (multiple wrap-around cannot occur with (Rn)+,
(Rn)- and -(Rn) addressing modes). The range of values for Nn is -2,147,483,648 to +2,147,483,647.
This type of address modification is useful for decimation, interpolation and waveform generation since the
multiple wrap-around capability may be used for argument reduction.
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DSP96002 USER'S MANUAL
MOTOROLA
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