Motorola DSP96002 User Manual page 61

Mantissa................ i.f = 1.00...00
NaNs (Not-a-Number):
s ...................... Don't care
Bias of e .............. n.a.
e ...................... 2047 ($7FF)
i ...................... 1
f ...................... Non-Zero
Mantissa................ i.f: 1.11...11 Legal QNaN
5.3.2 Address Generation Unit (AGU) Registers
The notation Rn will be used to designate one of the 8 address registers R0-R7. The notation Nn will be
used to designate one of the 8 address offset registers N0-N7. The notation Mn will be used to designate
one of the 8 address modifier registers M0-M7. The eight AGU address registers R0-R7 support address
or data operands of 32 bits. The eight AGU offset registers N0-N7 support offsets of 32 bits or may support
address or data operands of 32 bits. The eight AGU modifier registers M0-M7 support modifiers of 32 bits
or may support address or data operands of 32 bits.
5.3.3 Program Control Registers
The operating mode register (OMR) is 32 bits wide and may be accessed as a byte or word operand. The
status register (SR) is 32 bits wide with the system mode register (MR) occupying the high-order 8 bits, the
IEEE exception register (IER) occupying the next 8 bits, the exception register (ER) occupying the following
8 bits and the user condition code register (CCR) occupying the low-order 8 bits. The SR register may be
accessed as a word operand. The MR, IER, ER and CCR registers may be accessed as byte operands.
The loop counter register (LC), loop address register (LA), system stack pointer (SP), system stack high
(SSH), and system stack low (SSL) are 32 bits wide and may be accessed as word operands.
The program counter register (PC) is a special 32-bit wide program control register. It is always referenced
implicitly as a word operand.
The system stack is 64 bits wide and supports the concatenated PC and SR registers (PC:SR) for subrou-
tine calls, interrupts and program looping, and also supports the concatenated LA and LC registers (LA:LC)
for program looping.
5.4 NOT-A-NUMBER IMPLEMENTATION
When created by the DSP96002, Quiet Not-a-Numbers (QNaNs) represent the result of operations that
have no mathematical interpretation (e.g. zero multiplied by infinity) or the result of operations involving a
NaN operand as input.
Two different types of NaNs are implemented, differentiated by the most significand bit (MSB) of the frac-
tion. NaNs with the most significant bit of the fraction set to one are quiet NaNs (QNaNs), also called non-
signaling NaNs. NaNs with the most significant fraction bit equal to zero are signaling NaNs (SNaNs). The
DSP96002 never creates a SNaN as a result of an operation.
The DSP96002 legal QNaN is defined as follows:
5 - 8
1.1x...xx QNaN
1.0x...xx SNaN
DSP96002 USER'S MANUAL MOTOROLA