Motorola DSP96002 User Manual page 470

NEGC
Operation:
0 - D.L - C D.L (parallel data bus move)
Description:
Subtract the low portion of the destination operand D from zero along with the C bit of the condition code
register and store the result in the low portion of D. This instruction is useful when negating a multiple
precision number since it is not necessary to first zero an input operand as would be the case if the SUB
instruction were used. Note that the higher precision long words of the input variable must first be moved
to the lower portion of the Dn.
Input Operand(s) Precision: 32-bit integer.
Output Operand Precision: 32-bit integer.
CCR Condition Codes:
C
V
Z
N
I
LR
–
R
A
ER Status Bits: Not affected.
IER Flags: Not affected.
Instruction Format: NEGC
31
DATA BUS MOVE FIELD
OPTIONAL EFFECTIVE ADDRESS EXTENSION OR IMMEDIATE LONG DATA
Instruction Fields:
D
Dn.L
Timing: 2 + mv oscillator clock cycles
Memory: 1 + mv program words
A - 282
Negate with Carry
- Set if a borrow is generated from the MSB of the result. Cleared otherwise.
- Set if result overflows. Cleared otherwise.
- Cleared if the result is not zero. Unchanged otherwise.
- Set if result is negative. Cleared otherwise.
- Not affected.
- Not affected.
- Not affected.
- Not affected.
D ( See the MOVE instruction description.)
(u u)
d d d
n n n where nnn = 0-7
DSP96002 USER'S MANUAL
Assembler Syntax:
NEGC D
( See the MOVE instruction description.)
14 13
10 0001
NEGC
0
uu11 1ddd
MOTOROLA