Motorola DSP96002 User Manual page 104

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H R H A H
x 1 1
x 1 0
x 1 0
x 1 0
x 1 0
x 1 0
x 1 0
x 1 0
x 1 0
x 1 0
x 1 0
x 1 0
x 1 0
x 1 0
x 1 0
x 1 0
x 1 0
x 1 0
x 1 0
x 1 0
x 1 0
x 1 0
0 0 x
0 0 x
1 0 x
x 0 x
x 0 x
x 0 x
x 0 x
7.4.8 Host Control Register (HCR) - DSP96002 Side
The Host Control Register (HCR) is a 32-bit read/write control register used by the DSP96002 to control the
HI interrupts and flags. HCR cannot be accessed by the host processor. HCR is a read/write register to allow
the use of bit manipulation instructions on control register bits.
7.4.8.1 HCR Host Receive Interrupt Enable (HRIE) Bit 0
The Host Receive Interrupt Enable (HRIE) bit is used to enable the Host Receive Data interrupt when the
Host Receive Data Full (HRDF) status bit in the Host Status register (HSR) is set. When HRIE is cleared,
HRDF interrupts are disabled. When HRIE is set, the Host Receive Data interrupt request will occur if HRDF
is set. HRIE is cleared by HW/SW reset.
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SR/ WA5-A2Host Function
x xxxx Host Interface disabled
1 1000 ICS register read
0 1000 ICS register write
1 1001 SEM register read
0 1001 SEM register write
1 1010 RX register read
0 1010 TX register write
x 1011 Reserved
1 1100 IVR register read
0 1100 IVR register write
1 1101 CVR register read
0 1101 CVR register write
x 1110 Reserved
x 1111 Reserved
0 0000 TX register write and Y Memory Write interrupt
0 0001 TX register write and Y Memory Read
0 0010 TX register write and X Memory Write interrupt
0 0011 TX register write and X Memory Read
0 0100 TX register write and P Memory Write interrupt
0 0101 TX register write and P Memory Read
0 011x Reserved
1 0xxx Reserved
1 xxxx IVR read (DMAE=0) - 68K Interrupt Acknowledge
0 xxxx Reserved (DMAE=0)
x xxxx Reserved (DMAE=0)
x xxxx RX read
x xxxx TX write (DMA Mode: DMAE=1,TREQ=1,RREQ=0)
x xxxx Reserved (DMA Mode: DMAE=1,TREQ=0,RREQ=0)
x xxxx Reserved (DMA Mode: DMAE=1,TREQ=1,RREQ=1)
Figure 7-12. HI Functions
DSP96002 USER'S MANUAL
(DMA Mode: DMAE=1,TREQ=0,RREQ=1)
interrupt
interrupt
interrupt
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