Motorola DSP96002 User Manual page 108

7.4.9.6 HSR Reserved bits (Bits 5, 6, 14-31)
These status bits are reserved for future expansion and read as zero during DSP96002 read operations.
7.4.9.7 HSR DMA Status (HDMA) Bit 7
The DMA Status bit (HDMA) indicates that the host processor has enabled the external DMA handshake
mode of the HI. When HDMA is cleared, it indicates that the DMA Mode is disabled (DMAE=0) in the Inter-
rupt Control Register ICS. When HDMA is set, it indicates that the DMA Mode is enabled (DMAE=1).
Cleared by HW/SW reset.
7.4.9.8 HSR Host P Memory Read Command Pending (HPRP) Bit 8
The Host P Memory Read Command Pending (HPRP) bit indicates that the HRX register contains data from
the host processor written by the host processor via the host function "TX register write and P Memory Read
interrupt". HPRP is set when data is transferred from the TX register to the HRX register. HPRP is cleared
when the HTXC register is written by the DSP96002. HPRP is cleared by INIT (TREQ=1), HOST reset, and
HW/SW reset.
7.4.9.9 HSR Host P Memory Write Command Pending (HPWP) Bit 9
The Host P Memory Write Command Pending (HPWP) bit indicates that the HRX and TX registers contain
data from the host processor written by the host processor via the host function "TX register write and P
Memory Write interrupt". HPWP is set when the host processor writes TX for the second time consecutively
using this host function. HPWP is cleared when the HRX register is read twice consecutively (once for ad-
dress and once for data) by the DSP96002. HPWP is cleared by INIT (TREQ=1), HOST reset, and HW/SW
reset.
7.4.9.10 HSR Host X Memory Read Command Pending (HXRP) Bit 10
The Host X Memory Read Command Pending (HXRP) bit indicates that the HRX register contains data from
the host processor written by the host processor via the host function "TX register write and X Memory Read
interrupt". HXRP is set when data is transferred from the TX register to the HRX register. HXRP is cleared
when the HTXC register is written by the DSP96002. HXRP is cleared by INIT (TREQ=1), HOST reset, and
HW/SW reset.
7.4.9.11 HSR Host X Memory Write Command Pending (HXWP) Bit 11
The Host X Memory Write Command Pending (HXWP) bit indicates that the HRX and TX registers contain
data from the host processor written by the host processor via the host function "TX register write and X
Memory Write interrupt". HXWP is set when the host processor writes TX for the second time consecutively
using this host function. HXWP is cleared when the HRX register is read twice consecutively (once for ad-
dress and once for data) by the DSP96002. HXWP is cleared by INIT (TREQ=1), HOST reset, and HW/SW
reset.
7.4.9.12 HSR Host Y Memory Read Command Pending (HYRP) Bit 12
The Host Y Memory Read Command Pending (HYRP) bit indicates that the HRX register contains data from
the host processor written by the host processor via the host function "TX register write and Y Memory Read
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