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External DMA Controller
Bus Master
DMA Request
Bus Master
Write Bus Cycle
from Memory
Figure 7-19. External DMA to DSP96002 Data Write
should be cleared. Figure 7-19 contains a diagram showing the data paths and control lines used for the
data transfers.
A data write transfer is initiated when the slave's
is empty and ready to receive a data word from the master.
master which is a DMA service request input. When
fers the data word from memory to the TX register in the HI. The TX register is written by asserting
and TREQ=1 and RREQ=0. After TX is written (negating
HRX register, setting HRDF and TXDE. Setting TXDE causes
the slave's on-chip DMA Controller, HRDF is defined as a DMA service request signal. When HRDF is set,
the slave's on-chip DMA Controller initiates a data transfer from HRX to the slave memory, completing the
data transfer.
7.4.20.2
Data Read Using the DSP96002 On-Chip DMA Controller
This example outlines the steps that an external DMA Controller, the bus master, takes to transfer data from
a DSP96002 bus slave, thorough the slave's HI. The on-chip DMA Controller of the DSP96002 is used to
locally transfer data between the HI and the DSP96002 memory without interfering with core processing.
The TREQ and RREQ bits in the ICS register must be programmed to define the direction of data transfer
as being from the HI to the external DMA Controller (TREQ=0, RREQ=1). The TYEQ bit in the ICS register
should be cleared. Figure 7-20 contains a diagram showing the data paths and control lines used for the
data transfers.
MOTOROLA
empty
—
—
–
R
E
Q
—
—
–
A
C
K
data
—
DSP96002 USER'S MANUAL
DSP96002
Bus Slave
—
—
D0–D31
–
H
R signal is asserted, indicating that its HI TX register
—
–
H
R is connected to a
—
–
H
R is asserted, the external DMA Controller trans-
—
–
H
R), the data is transferred by the HI to the
—
–
H
R to be asserted since TREQ is set. In
–
DMA Request
H
R
Host
Memory
DMA Transfer
Transmit Data
Empty (TXDE=1)
–
H
A
Host Data Full
(HRDF=1)
—
—
–
R
E
Q pin in the
—
–
H
A
7 - 35
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