Motorola DSP96002 User Manual page 310

FJcc Floating-Point Jump Conditionally
Operation:
If cc, then xx PC
else PC+1 PC
If cc, then ea PC
else PC+1 PC
Description:
If the specified floating-point condition is true, program execution then continues at a location specified by
an effective address in the instruction. If the specified condition is false, the PC is incremented and the
effective address is ignored. However, the address register specified in the effective address field is al-
ways updated independently of the condition. All memory alterable addressing modes may be used for
the effective address. A Fast Short Jump addressing mode may also be used. The 15-bit data is sign
extended to form the effective address. See Section A.10 for restrictions. Non-aware floating-point con-
ditions set the SIOP flag in the IER register and the UNCC bit in the ER register if the NAN bit is set.
"cc" may specify the following conditions:
Mnemonic
EQ
ERR
GE
GL
GLE
GT
INF
LE
LT
MI
NE(Q) - not equal
NGE
NGL
NGLE - not(greater, less or equal) NAN = 1
NGT
NINF - not infinity
NLE
NLT
OR
PL
UN
Note: The operands for the ERR condition are taken from the ER register.
* See the description of the UNcc bit in Section A.4.
A - 122
- equal
- error
- greater than or equal
- greater or less than
- greater, less or equal
- greater than
- infinity
- less than or equal
- less than
- minus
- not(greater than or equal) NAN v (N & ~Z) = 1
- not(greater or less than)
- not greater than
- not(less than or equal)
- not less than
- ordered
- plus
- unordered
DSP96002 USER'S MANUAL
Assembler Syntax:
FJcc label (short)
FJcc ea
Condition
Z = 1
UNCC v SNAN v OPERR v No
OVF v UNF v DZ = 1
NAN v (N & ~Z) = 0
NAN v Z = 0
NAN = 0
NAN v Z v N = 0
I = 1
NAN v ~(N v Z) = 0
NAN v Z v ~N = 0
N = 1
Z = 0
NAN v Z = 1
NAN v Z v N = 1
I = 0
NAN v ~(N v Z) = 1
NAN v Z v ~N = 1
NAN = 0
N = 0
NAN = 1
FJcc
Non-aware
Set UNCC*
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
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