Motorola DSP96002 User Manual page 130

The table in Figure 7-24 shows the data transfers that the DMA Controller is capable of. The number of cy-
cles specified in the Figure 7-24 notes are for the operation of one channel using a continuous block trans-
fer.
Int. mem
Int. mem
Ext. mem
Ext. mem
Ext. mem
Int. mem
Int. mem
Ext. mem
Ext. mem
Int. I/O
Notes:
Two clock cycles for every word.
1.
2. Four clock cycles for every word (the same address bus is used for source and destination).
Four clock cycles for every word.
3.
7 - 44
DMA data transfers
Int. mem (different memory space)
Int. mem (same memory space)
Int. mem (different memory space)
Int. mem (same memory space)
Ext. mem
Int. I/O (different memory space)
Int. I/O (same memory space)
Int. I/O (different memory space)
Int. I/O (same memory space)
Int. I/O
Figure 7-24. Direction of DMA Data Transfers
DSP96002 USER'S MANUAL
Notes
#1
#2
#1
#2
#3
#1
#2
#1
#2
#2
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