Motorola DSP96002 User Manual page 13

register (IVR) onto the data bus outputs D0-D31. This provides an interrupt acknowl-
edge capability compatible with MC68000 family processors.
If the host interface is in DMA mode,
put and it is asserted by an external device to transfer data between the Host Interface
registers and an external device. In DMA read mode,
Interface RX register on the data bus outputs D0-D31. In DMA write mode,
serted to strobe external data into the Host Interface TX register. Write data is latched
into the TX register on the rising edge of
— –
H R (Host Request) - active low output, never three-stated. The host request
serted to indicate that the host interface is requesting service - either an interrupt request
or a DMA request - from an external device.
The
–
Q B, or
channel can select the interrupt request input as a DMA transfer request input.
— –
B R (Bus Request) - active low output, never three-stated.
or DMA is requesting bus mastership.
longer needs the bus.
the DSP96002 is a bus master or a bus slave. Bus "parking" allows
deasserted even though the DSP96002 is the bus master. See the description of bus
"parking" in the
Section seven) allows
CPU or DMA does not need the bus.
which controls the priority, parking and tenure of each DSP96002 on the same external
bus.
internal bus. During hardware reset,
to the bus slave state.
— –
B G (Bus Grant) – active low input.
input clock (CLK) for proper operation.
circuit when the DSP96002 may become the next bus master. When
the DSP96002 must wait until
— –
B
cycle. This may occur in the middle of an instruction which requires more than one ex-
ternal bus cycle for execution. Note that indivisible read-modify-write instructions
2 - 10
— –
H R output may be connected to interrupt request input
— — — –
I R Q C of another DSP96002. The DSP96002 on-chip DMA Controller
— –
B
— –
B A pin description. The RH bit in the Bus Control Register (see
— –
B
— –
B R is only affected by CPU or DMA requests for the external bus, never for the
G is deasserted, bus mastership is typically given up at the end of the current bus
DSP96002 USER'S MANUAL
— –
H A is used as a DMA transfer acknowledge in-
— –
H A.
— –
B R is deasserted when the CPU or DMA no
R may be asserted or deasserted independent of whether
R to be asserted under software control even though the
— –
B R is typically sent to an external bus arbitrator
— –
B R is deasserted and the arbitration is reset
— –
B G must be asserted/ deasserted synchronous to the
— –
B G is asserted by an external bus arbitration
— –
B B is deasserted before taking bus mastership. When
— –
H A is asserted to read the Host
—
—
— — — –
I R Q A,
— –
B R is asserted when the CPU
—
— –
B G is asserted,
MOTOROLA
–
H A is as-
–
H R is as-
— — —
I R
–
B R to be