Motorola DSP96002 User Manual page 94

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T T Pin Activity for
PE XE YE P Space
0 0 0 Deasserted
0 0 1 Deasserted
0 1 0 Deasserted
0 1 1 Deasserted
1 0 0 Active
1 0 1 Active
1 1 0 Active
1 1 1 Active
7.2.2.2 Refresh Faults
There is no internal support for refresh timers, refresh address counters or refresh faults which should deas-
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sert T T. The page circuit assumes that refresh does not exist and therefore
by the external memory controller based on its knowledge of refresh timing and external bus activity. The
use of multiple processors with the same external DRAM/VRAM indicates that the memory controller is the
best place to enforce refresh priorities. With the variety of refresh techniques based on the expected mem-
ory activity, the external memory controller state machine is the best place to have global control over re-
fresh timing and arbitration caused by multiple access conflicts. At the end of each external bus cycle, the
external memory controller should determine if it should begin a refresh cycle. If yes, it will disable the trans-
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fer acknowledge T A signal to ensure that the DSP96002 waits if it begins an external access. Once the
refresh is completed, the external memory controller must remember to ignore the
memory cycle so that a fast access mode is not used. The external state machine should cancel (ignores)
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the effect of the T T signal in the next external bus cycle after any hardware refresh operation. Note that
if fast interrupts are used to implement a software refresh, refresh looks like a memory read cycle so no
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special treatment of T
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7.2.2.3 R A
Since DRAM/VRAM devices are dynamic, there are maximum limits on the
time which must be observed. To effectively use the fast access modes with the DSP96002, the external
state machine must keep
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modes. C A S must remain asserted between bus cycles for static column mode only. However, if no
external access occurs after the external state machine is ready for a fast access mode, there is a possibility
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that R A S or C
tive" to use the fast access modes with the DSP96002 non-burst, random address bus cycles. The
DSP96002 does not provide any internal support for
7 - 8
X Space
Deasserted
Deasserted
Active
Active
Deasserted
Deasserted
Active
Active
Figure 7-5. Memory Space Enables Encoding
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T is needed.
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S, C A S and SC Timeout Faults
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R A S asserted between bus cycles for page, nibble and static column
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A S may "timeout". This is because the idle memory state must be "
DSP96002 USER'S MANUAL
Current Bus Cycle Latched for
Y Space P Space
Deasserted No
Active No
Deasserted No
Active No
Deasserted Yes
Active Yes
Deasserted Yes
Active Yes
— — – — — –
R A S or C A
X Space Y Space
No No
No Yes
Yes No
Yes Yes
No No
No Yes
Yes No
Yes Yes
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T T must be interpreted
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T T signal for the next
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R A S and C A
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R A
S timeouts. The external state
MOTOROLA
S low
–
S ac-