Motorola DSP96002 User Manual page 98

The HI appears as a memory mapped peripheral occupying 16 locations in the host processor address
space. Separate transmit and receive data registers are double-buffered to allow the DSP96002 and host
processor to efficiently transfer data at high speed. Host processor communication with the HI registers is
accomplished using standard host processor instructions and addressing modes.
Handshake flags are provided for polled or interrupt-driven data transfers with a host processor.
External DMA controllers (e.g. MC68450) are able to perform block data transfers between the DSP96002
HI and the external host processor memory. For this purpose, a "DMA mode" is provided in the HI. In this
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mode, the H A pin is used to enable access to the transmit/receive registers in the HI, without regard to
the status of the address lines A2-A5.
The host processor can also issue vectored exception requests to the DSP96002 with the host command
feature. The host processor may select any of the 256 DSP96002 exception routines to be executed by writ-
ing a vector address register. This flexibility allows the host processor programmer to execute a wide num-
ber of preprogrammed functions inside the DSP96002. Host exceptions can allow the host processor to
read or write DSP96002 registers, X, Y, or Program memory locations and perform control and debugging
operations if exception routines are implemented in the DSP96002 to do these tasks.
The DSP96002 views the HI as a memory mapped peripheral occupying four 32-bit words in X data memory
space. The DSP96002 may use the HI as a normal memory-mapped peripheral using standard polled or
interrupt programming techniques.
7.4.2 HI Reset
The HI is affected by the following types of reset:
HW/SW Reset Hardware (HW) reset, generated by asserting the
(SW) reset, generated by executing the RESET instruction. Status and control bits in
the HI are affected as defined in Figure 7-7 and Figure 7-8.
HOST Reset HI personal reset, generated when the HRES bit in the HCR register is set. Only HI sta-
tus bits are affected as defined in Figure 7-7 and 7-8. Only the DSP96002 may directly
activate the HOST Reset since HRES is located in the DSP96002 side. Note that the
HI remains in this state as long as the HRES bit is set. The HRES bit is not self-clearing.
INIT HI personal reset, generated when the INIT bit in the ICS register is set. Only HI status
bits are affected as defined in Figure 7-7 and Figure 7-8. Note that INIT may selectively
reset the transmit and/or the receive channel(s) according to the state of the TREQ and
RREQ control bits in the ICS register. Also, the INIT bit is self-clearing, in contrast to
the HRES bit which requires an explicit clear operation.
7.4.3 HI Operation During Stop
The host processor is able to read/write the HI registers when the DSP96002 is in the Stop state (see Sec-
tion 8). If the clock is stopped in the middle of a host processor access, the flag setup and data transfer
across the HI will be frozen. The transfer and flag setup will finish after the clock is restarted.
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