Motorola DSP96002 User Manual page 11

When a bus master, the combination of
determine the status of the current bus cycle and to generate hardware strobes useful
for latching address and data signals. The encoding is shown in Figure 2-4.
t0 t1
CLK
— –
B
— –
T S
— –
A
— –
D
—
B
1
0
0
1
Figure 2-4. Bus Status Encoding
— –
T A (Transfer Acknowledge) - active low input. If the DSP96002 is the bus master and either
there is no external bus activity or the DSP96002 is not the bus master, the
is ignored by the core. The
extend an external bus cycle indefinitely.
chronous to the input clock (CLK) for proper operation.
edge of the input clock (CLK). Any number of wait states (0, 1, 2, ..., infinity) may be
inserted by keeping
start of a bus cycle, is asserted to enable completion of the bus cycle and is deasserted
before the next bus cycle. The current bus cycle completes one clock period after
A is asserted synchronous to CLK. The number of wait states is determined by the
–
T A input or by the Bus Control Register (BCR), whichever is longer. The BCR can be
used to set the minimum number of wait states in external bus cycles. If
low (asserted) and no wait states are specified in the BCR register, zero wait states will
be inserted into external bus cycles.
2 - 8
t2 t3 t0
– — –
S T S Bus Status Strobe Generation Application
1 Idle
1 Cycle Start Address Strobe (
0 Wait
0 Cycle End Data Strobe (
— –
T A deasserted. In typical operation,
DSP96002 USER'S MANUAL
— – —
B S and
WS
t1 t2 tw
— –
A S)
— –
D S)
— –
T A input is a synchronous "DTACK" function which can
— –
T A must be asserted and deasserted syn-
–
T S can be decoded externally to
WS
t2 tw t2 t3
—
— –
T A is sampled on the falling
— –
T A is deasserted at the
—
MOTOROLA
––
T A input
— –
T
—
–
T A is tied