Motorola DSP96002 User Manual page 180

through the serial interface. This register is affected by the operations performed during the Debug Mode
and must be restored by the command controller when returning to normal mode.
10.8.3 PIL Register (OPILR)
The PIL Register is a 32-bit latch that stores the value of the Instruction Latch before the Debug Mode is
entered. OPILR can only be read through the serial interface. This register is affected by the operations per-
formed during the Debug Mode and must be restored by the command controller when returning to normal
mode. Since there is no direct access to this register, this task is accomplished by writing the OPDBR first
and then the data from OPDBR is latched in OPILR.
10.8.4 GDB Register (OGDBR)
The GDB Register is a 32-bit latch that can only be read through the serial interface. OGDBR is not actually
required from a pipeline status restore point of view but is required as a means of passing information be-
tween the chip and the command controller. OGDBR is mapped on the X internal I/O space at address
$FFFFFFF0. Whenever the command controller needs a data word such as a register or memory value, it
will force the chip to execute an instruction that brings that information to OGDBR. Then, the contents of
OGDBR will be delivered serially to the command controller by the command "READ GDB REGISTER".
10.9 PAB HISTORY BUFFER
To ease the debugging activity and keep track of the program flow, a First-In-First-Out buffer is provided
which stores the addresses of the last five instructions that were executed as well as the addresses of the
last fetched instruction and of the instruction currently in the Instruction Latch.
10 - 14
Figure 10-7. Pipeline Information Registers
DSP96002 USER'S MANUAL MOTOROLA