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—
–
If
H
R is used and the host processor reads RX or writes TX when the DSP96002 is in the Stop state,
—
–
then
H
R will only be deasserted after exiting the Stop state. .
Register
Register
Name
Contents
ICS
HMRC
HRST
DMAE
HF3-HF2
HF1-HF0
HREQ
INIT
TYEQ
TREQ
RREQ
TRDY
TXDE
RXDF
CVR
HC
HV7-HV0
IVR
IV7-IV0
SEM
SEM(15-0)
Notes:
1. HREQ = TYEQ + TREQ
2. HREQ = (TYEQ & TRDY) + (TREQ & TXDE)
Symbols:
HW - Hardware Reset caused by asserting the external pin
SW - Software Reset caused by executing the RESET instruction.
HOST - Host Personal Reset caused when HRES=1.
INIT - Host Personal Reset caused when INIT=1.
"1" - The bit is set.
"0" - The bit is cleared.
"-" - The bit is not affected.
"+" - Logical OR operation.
"&" - Logical AND operation.
Figure 7-7. Host Interface Reset - Host Processor Side
MOTOROLA
HW/SW
HOST
Reset
Reset
0
0
1
1
0
-
0
-
0
-
0
Note 1
0
-
0
-
0
-
0
-
1
1
1
1
0
0
0
-
$0E
-
$0F
-
$0F
-
$0000
-
DSP96002 USER'S MANUAL
INIT
INIT
TREQ=1
TREQ=0
RREQ=0
RREQ=1
0
-
-
-
-
-
-
-
-
-
1
Note 2
0
0
-
-
1
0
0
1
1
-
1
-
-
0
-
-
-
-
-
-
-
-
-
-
—
—
R
INIT
Comments
TREQ=1
RREQ=1
0
-
-
-
-
1
0
-
1
1
1
1
0
-
-
port A
-
port B
-
-
—
—
–
E
S
E
T.
7 - 13
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