Motorola DSP96002 User Manual page 304

FDEBUGcc
Operation:
If cc, then enter debug mode.
Description:
If the specified floating-point condition is true, enter Debug mode and wait for OnCE
specified condition is false, continue with the next instruction. Non-aware floating-point conditions set the
SIOP flag in the IER register and the UNCC bit in the ER register if the NAN bit is set.
"cc" may specify the following conditions:
Mnemonic
EQ
ERR
GE
GL
GLE
GT
INF
LE
LT
MI
NE(Q) - not equal
NGE
NGL
NGLE - not(greater, less or equal) NAN = 1
NGT
NINF - not infinity
NLE
NLT
OR
PL
UN
Note: The operands for the ERR condition are taken from the ER register.
* See description of the UNcc bit in Section A.4.
CCR Condition Codes: Not affected.
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A - 116
Enter Debug Mode
Conditionally
- equal
- error
- greater than or equal
- greater or less than
- greater, less or equal
- greater than
- infinity
- less than or equal
- less than
- minus
- not(greater than or equal) NAN v (N & ~Z) = 1
- not(greater or less than)
- not greater than
- not(less than or equal)
- not less than
- ordered
- plus
- unordered
DSP96002 USER'S MANUAL
Assembler Syntax:
FDEBUGcc
Condition
Z = 1
UNCC v SNAN v OPERR v No
OVF v UNF v DZ = 1
NAN v (N & ~Z) = 0
NAN v Z = 0
NAN = 0
NAN v Z v N = 0
I = 1
NAN v ~(N v Z) = 0
NAN v Z v ~N = 0
N = 1
Z = 0
NAN v Z = 1
NAN v Z v N = 1
I = 0
NAN v ~(N v Z) = 1
NAN v Z v ~N = 1
NAN = 0
N = 0
NAN = 1
FDEBUGcc
commands. If the
Non-aware
Set UNCC*
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
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