Motorola DSP96002 User Manual page 511

A.9.7 LEA Timing Summary
If there are wait states, (i.e., assumption 4 is not applicable) then to each 1-word instruction timing a "+ap"
term should be added and to each 2-word instruction a "+(2 * ap)" term should be added to account for the
program memory wait states spent to fetch an instruction word to fill the pipeline.
A.9.8 LRA Timing Summary
If there are wait states, (i.e., assumption 4 is not applicable) then to each 1-word instruction timing a "+ap"
term should be added and to each 2-word instruction a "+(2 * ap)" term should be added to account for the
program memory wait states spent to fetch an instruction word to fill the pipeline.
A.9.9 Bit Manipulation Timing Summary
Bit Manipulation
Operation
Bxxx I/O Short
Bxxx Absolute Short
Bxxx Register Direct
Bxxx X Memory
Bxxx Y Memory
BTST I/O Short
BTST Absolute Short
BTST Register Direct
BTST X Memory
BTST Y Memory
Figure A-16 Bit Manipulation Timing Summary
MOTOROLA
MOVEC Operation
Update Addressing Modes
Long Displacement
Figure A-14 LEA Timing Summary
LRA Operation
PC Relative Long Displacement
PC Relative Address Reg.
Figure A-15 LRA Timing Summary
+ mvb
Cycles
2 * aio
0
0
ea + (2 * ax)
ea + (2 * ay)
aio
0
0
ea + ax
ea + ay
DSP96002 USER'S MANUAL
+ le
Cycles Comments
0
2
+ lr + lr
Words Cycles
1 2
0 0
where Bxxx = BCHG, BCLR or BSET
where Bxxx = BCHG, BCLR or BSET
where Bxxx = BCHG, BCLR or BSET
where Bxxx = BCHG, BCLR or BSET
where Bxxx = BCHG, BCLR or BSET
A - 323