Motorola DSP96002 User Manual page 433

Move
FFcc.U
Operation:
If cc, then opcode operation
S D
Description:
If the specified floating-point condition is true, transfer data from the specified source S to the specified
destination D. Also, store result(s) of the specified Data ALU operation and update the CCR, ER and IER
registers with the status information generated by the Data ALU operation. If the specified condition is
false, no destinations are altered and the status register is not affected by the Data ALU operation. The
UNCC bit in the ER register and SIOP flag in the IER are set by the FFcc.U instruction if the NAN bit in the
ER register was set and the specified condition is one of the conditions with a "Yes" entry in the "Set UN-
CC" column. If no register move is specified, this instruction is assembled with a R0 to R0 move.
"cc" may specify the following conditions:
Mnemonic
EQ
ERR
GE
GL
GLE
GT
INF
LE
LT
MI
NE(Q)
NGE
NGL
NGLE
NGT
NINF
NLE
NLT
OR
PL
UN
Note: The operands for the ERR condition are taken from the ER register.
* See description of UNcc bit in Section A.4.
MOTOROLA
Floating-Point iF
Conditional Instruction
with CCR, ER, IER Update
- equal
- error
- greater than or equal
- greater or less than
- greater, less or equal
- greater than
- infinity
- less than or equal
- less than
- minus
- not equal
- not(greater than or equal)NAN v (N & ~Z) = 1
- not(greater or less than) NAN v Z = 1
- not(greater, less or equal)NAN = 1
- not greater than
- not infinity
- not(less than or equal)
- not less than
- ordered
- plus
- unordered
DSP96002 USER'S MANUAL
Assembler Syntax:
Opcode-Operands S,D
Condition
Z = 1
UNCC v SNAN v OPERR v No
OVF v UNF v DZ = 1
NAN v (N & ~Z) = 0
NAN v Z = 0
NAN = 0
NAN v Z v N = 0
I = 1
NAN v ~(N v Z) = 0
NAN v Z v ~N = 0
N = 1
Z = 0
NAN v Z v N = 1
I = 0
NAN v ~(N v Z) = 1
NAN v Z v ~N = 1
NAN = 0
N = 0
NAN = 1
Move
FFcc.U
FFcc.U
FFcc.U
Non-aware
Set UNCC*
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
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