Motorola DSP96002 User Manual page 835

7.4 Interrupt Priority Register (IPR)
The Interrupt Priority Register supports the timer module with the addition of the Timer0
and Timer1 priority level bits. Figure 21 shows the revised IPR with the new bits indicated
in bold characters.
** **
HBL1 HBL0 HAL1 HAL0 D1L1 D1L0 D0L1 D0L0
**
**
IRBS IBL2 IBL1 IBL0 IRAS IAL2 IAL1 IAL0
Figure 21 - Interrupt Priority Register (Address X:$FFFFFFFF)
MOTOROLA
T1L1 T1L0
** **
IRCS ICL2 ICL1 ICL0
** **
T0L1 T0L0
Timer0 IPL
Timer1 IPL
Reserved
DMA Channel 0 IPL
DMA Channel 1 IPL
Host A IPL
Host B IPL
IRQC IPL
IRQC Trigger Mode
IRQC Status
Reserved
IRQA IPL
IRQA Trigger Mode
IRQA Status
IRQB IPL
IRQB Trigger Mode
IRQB Status
53