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ANDI
AND Immediate to Control Register
Operation:
D & #xx
D
Description:
Logically AND the contents of the control register with an 8-bit immediate operand. The result is stored
back into the specified control register. See Section A.10 for restrictions.
CCR Condition Codes:
For CCR operand:
C
- Cleared if bit 0 of the immediate operand is cleared. Not affected otherwise.
V
- Cleared if bit 1 of the immediate operand is cleared. Not affected otherwise.
Z
- Cleared if bit 2 of the immediate operand is cleared. Not affected otherwise.
N
- Cleared if bit 3 of the immediate operand is cleared. Not affected otherwise.
I
- Cleared if bit 4 of the immediate operand is cleared. Not affected otherwise.
LR
- Cleared if bit 5 of the immediate operand is cleared. Not affected otherwise.
–
R
- Cleared if bit 6 of the immediate operand is cleared. Not affected otherwise.
A
- Cleared if bit 7 of the immediate operand is cleared. Not affected otherwise.
For OMR, MR, IER, ER operands:
C
- Not affected.
V
- Not affected.
Z
- Not affected.
N
- Not affected.
I
- Not affected.
LR
- Not affected.
–
R
- Not affected.
A
- Not affected.
ER Status Bits:
For ER operand:
INX
- Cleared if bit 0 of the immediate operand is cleared. Not affected otherwise.
DZ
- Cleared if bit 1 of the immediate operand is cleared. Not affected otherwise.
UNF
- Cleared if bit 2 of the immediate operand is cleared. Not affected otherwise.
OVF
- Cleared if bit 3 of the immediate operand is cleared. Not affected otherwise.
OPERR - Cleared if bit 4 of the immediate operand is cleared. Not affected otherwise.
SNAN - Cleared if bit 5 of the immediate operand is cleared. Not affected otherwise.
NAN
- Cleared if bit 6 of the immediate operand is cleared. Not affected otherwise.
UNCC - Cleared if bit 7 of the immediate operand is cleared. Not affected otherwise.
MOTOROLA
Assembler Syntax:
AND(I) #Byte,D
DSP96002 USER'S MANUAL
ANDI
A - 25
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