Motorola DSP96002 User Manual page 352

32-bit digital signal processor
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FSEEDD
Operation:
Approximation(1/S)
D
Description:
Take the contents of the specified source operand S, determine an approximation to 1.0/S, and store the
result in the destination operand D. The 9 MSBs of the destination significand are determined by using a
lookup ROM. The remaining bits of the significand are zeroed. This instruction is useful for initializing
floating-point divide algorithms.
The table below describes the operation of the FSEEDD instruction:
Source Operand
SNaN or QNaN
+/- zero
+/- denormalized
+/- normalized
+/- infinity
Input Operand(s) Precision: SEP Floating-Point.
Output Operand Precision: SEP Floating-Point.
CCR Condition Codes:
C
V
Z
N
I
LR
R
A
A - 164
Reciprocal Approximation
Result
QNaN
+/- infinity
normalized, then FSEEDD approximation
FSEEDD approximation
+/- zero
- Not affected.
- Not affected.
- Set if result is zero. Cleared otherwise.
- Set if result is negative. Cleared otherwise.
- Set if result is infinity. Cleared otherwise.
- Not affected.
- Not affected.
- Not affected.
DSP96002 USER'S MANUAL
Assembler Syntax:
FSEEDD S,D
FSEEDD
MOTOROLA

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