Motorola DSP96002 User Manual page 204

Note 31 OPERR - Set if the source operand is less than zero. Cleared otherwise.
A.5 IEEE EXCEPTION BITS COMPUTATION
The IEEE Exception bits are the five exception bits required by the IEEE standard for trap disabled oper-
ations. They actually record a history of all floating-point exceptions which have occurred since the user
last cleared the IER register. At the end of each floating-point operation, the bits of the ER are logically
combined and then are logically ORed into the existing IER bits creating "sticky" floating-point exception
bits which can be polled at the end of a series of floating-point operations. The standard definition of the
IER bits and the complete IER exception flag computation rules are given below.
SINX (IEEE Inexact) - signaled when the rounded result of an operation is not exact or if it overflows
without an overflow trap.
SINX = SINX v (OVF v INX)
SDZ (IEEE Division by Zero) - signaled if the dividend is a finite nonzero number and the divisor is
zero.
SDZ = SDZ v DZ
SUNF (IEEE Underflow) - signaled when both tininess and loss of accuracy have been detected. Ti-
niness is detected before round (see definition of UNF in the ER register). Loss of accuracy is
detected as an inexact result (see definition of INX in the ER register).
SUNF = SUNF v (UNF & INX)
SOVF (IEEE Overflow) - signaled when the destination format largest finite number is exceeded in
magnitude by what would have been the rounded floating-point result were the exponent range
unbounded.
SOVF = SOVF v OVF
SIOP (IEEE Invalid Operation) - signaled if an operand is invalid for the operation to be performed.
SIOP = SIOP v (UNCC v SNAN v OPERR)
A.6 NOTATION
Symbols are used to abbreviate operands and operations in each instruction description. Figure A-6 lists
the symbols used and their respective meanings.
A - 16 DSP96002 USER'S MANUAL MOTOROLA