Motorola DSP96002 User Manual page 834

7.3 Exception Priorities within an IPL
If more than one exception is pending when an instruction is executed, the interrupt with
the highest priority level is serviced first. Within a given interrupt priority level, a second
priority structure determines which interrupt is serviced when multiple interrupt requests
with the same IPL are pending.
Priority
highest
lowest
52
Table 6 DSP96002 Exception Priorities within an IPL
Exception
Hardware RESET
Illegal Instruction
Stack Error
(F)TRAPcc
IRQA (External Interrupt)
IRQB (External Interrupt)
IRQC (External Interrupt)
Host A Command Interrupt
Host A Receive Data Interrupt
Host A Read X Memory Interrupt
Host A Read Y Memory Interrupt
Host A Read P Memory Interrupt
Host A Write X Memory Interrupt
Host A Write Y Memory Interrupt
Host A Write P Memory Interrupt
Host A Transmit Data Interrupt
Host B Command Interrupt
Host B Receive Data Interrupt
Host B Read X Memory Interrupt
Host B Read Y Memory Interrupt
Host B Read P Memory Interrupt
Host B Write X Memory Interrupt
Host B Write Y Memory Interrupt
Host B Write P Memory Interrupt
Host B Transmit Data Interrupt
DMA Channel 0 Interrupt
DMA Channel 1 Interrupt
Timer0 Interrupt
Timer1Interrupt
Enabled by
-
-
-
-
(IPR) IAL1-IAL0
(IPR) IBL1-IBL0
(IPR) ICL1-ICL0
(HCR) HCIE
(HCR) HRIE
(HCR) HXRE
(HCR) HYRE
(HCR) HPRE
(HCR) HXWE
(HCR) HYWE
(HCR) HPWE
(HCR) HTIE
(HCR) HCIE
(HCR) HRIE
(HCR) HXRE
(HCR) HYRE
(HCR) HPRE
(HCR) HXWE
(HCR) HYWE
(HCR) HPWE
(HCR) HTIE
(DCS0) DIE0
(DCS1) DIE1
(TCSR0) TIE0
(TCSR1) TIE1
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