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ICL2
Trigger Mode
0
level
1
negative edge
8.5.2.9 IRQC Status - IRCS (Bit 11)
The read-only IRQC Status (IRCS) bit indicates the status of the interrupt request for the external interrupt
input IRQC. If the IRQC interrupt is defined as edge-sensitive and it is enabled, the IRCS bit indicates
the state of the edge-detection latch. If the IRQC interrupt is defined as level-sensitive or is disabled,
the IRCS bit indicates the state of the IRQC pin after internal synchronization.
IRCS
Status (edge and enabled) IRQC pin (level or disabled)
0
Serviced
1
Pending
8.5.2.10
Reserved bits (Bits 12-15, 24-31)
These reserved bits read as zero and should be written with zero for future compatibility.
8.5.2.11 DMA Channel 0 Interrupt Priority Level - D0L1-D0L0 (Bits 16-17)
The DMA Channel 0 Interrupt Priority Level (D0L1-D0L0) bits are used to enable and specify the priority
level of the DMA Channel 0 interrupt.
D0L1 D0L0
0
0
0
1
1
0
1
1
8.5.2.12 DMA Channel 1 Interrupt Priority Level - D1L1-D1L0 (Bits 18-19)
The DMA Channel 1 Interrupt Priority Level (D1L1-D1L0) bits are used to enable and specify the priority
level of the DMA Channel 1 interrupt.
D1L1 D1L0
0
0
0
1
1
0
1
1
8.5.2.13
Host A Interrupt Priority Level - HAL1-HAL0 (Bits 20-21)
The Host A Interrupt Priority Level (HAL1-HAL0) bits are used to enable and specify the priority level of all
interrupt sources located in the Port A Host Interface.
8 - 14
High
Low
Enabled
Int. Priority Level (IPL)
no
-
yes
0
yes
1
yes
2
Enabled
Int. Priority Level (IPL)
no
-
yes
0
yes
1
yes
2
DSP96002 USER'S MANUAL
MOTOROLA
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