Motorola DSP96002 User Manual page 36

one instruction cycle. In the following cycle, the contents of TempR are used to address X or Y memory.
For all absolute addressing modes, the address of the operand is written into TempR and then used to ad-
dress X, Y, or P memory.
The temporary address registers TempN Low and TempN High are 32-bit registers which provide tempo-
rary storage for the PC loaded from the Program Address Bus and it is used in case of the PC relative ad-
dressing mode. They may also be loaded from the Program Data Bus in case of Long or Short Displace-
ment addressing mode.
3.4.5 Modulo Arithmetic Units
A block diagram of one modulo arithmetic unit is shown in Figure 3-4. The two modulo arithmetic units are
identical. Each contains a 32-bit full adder (called offset adder) which may add one, minus one, the contents
of the respective offset register N or the two's complement of N, to the contents of the selected address
register. A second full adder (called modulo adder) adds the summed result of the first full adder to a mod-
ulo value M or minus M, where M is stored in the respective modifier register. A third full adder (called re-
verse carry adder) adds the constant one, minus one, the offset N (stored in the respective offset register)
or minus N to the selected address register with the carry propagating in the reverse direction, i. e. from the
most significant bit to the least. The offset adder and the reverse carry adder are in parallel and share com-
mon inputs. The only difference between them is that the carry propagates in opposite directions. Test log-
ic, which consists of a modifier decoder, two carry multiplexers, and some control logic, determines which
of the three summed outputs of the full adders is output to its associated address register file or temporary
register.
Each modulo arithmetic unit can update one address register, Rn, from its respective address register file
during one instruction cycle. It is capable of performing linear, reverse carry, and modulo arithmetic. The
contents of the selected modifier register specifies the type of arithmetic to be used in an address register
update calculation. The modifier value is decoded in the modulo arithmetic unit and affects the unit's oper-
ation. The modulo arithmetic unit's operation is data-dependent and requires execution cycle decoding of
the selected modifier register contents. The modulo arithmetic unit performs three operations in parallel:
1. The output of the offset adder gives the result of linear arithmetic (e.g. Rn+1; Rn+Nn) and is
selected as the modulo arithmetic unit's output for linear arithmetic addressing modifiers and
PC relative addressing modes.
2. The reverse carry adder performs the required operation for reverse carry arithmetic and its
output is selected as the modulo arithmetic unit's output for reverse carry addressing modifiers.
Reverse carry arithmetic is useful for 2**K point Radix 2 FFT addressing. For modulo arith-
metic, the modulo arithmetic unit will perform the function (Rn+/-N) modulo M where N can be
one, minus one, or the contents of the offset register Nn.
3. If the modulo operation requires wraparound for modulo arithmetic, the summed output of the
modulo adder will give the correct updated address register value; otherwise, if wraparound is
not necessary, the output of the offset adder gives the correct result.
The test logic determines which output address to select. Modulo arithmetic units are shared by the DMA
and the AGU and they are time multiplexed.
3.4.6 Address Output Multiplexers
The address output multiplexers select the source for the XAB, YAB, and PAB. They allow the XAB, YAB,
or PAB address outputs to originate from either R0-R3, R4-R7, or from TempR Low or TempR High. The
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